公开(公告)号：US08759834B2

公开(公告)日：2014-06-24

申请号：US13947459

申请日：2013-07-22

Applicant: Samsung Display Co., Ltd.

Inventor： Joo-Ae Youn ,  Yang-Ho Bae ,  Chang-Oh Jeong ,  Chong-Chul Chai ,  Pil-Sang Yun ,  Hong Long Ning ,  Byeong-Beom Kim

IPC: H01L21/33

CPC classification number: H01L33/0041 ,  H01L27/124 ,  H01L29/458

Abstract: A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT.

Abstract translation: 显示面板包括： 下栅极线，基本上垂直于下栅极线设置的下数据线，连接到下栅极线和下数据线的薄膜晶体管（“TFT”），设置在下栅极线上的绝缘层， 下数据线和TFT，并且具有暴露下栅极线和下数据线的多个沟槽，设置在下栅极线上的沟槽中的上栅极线，设置在下数据上的沟槽中的上数据线 线和与TFT连接的像素电极。

公开(公告)号：US08847228B2

公开(公告)日：2014-09-30

申请号：US13691307

申请日：2012-11-30

Applicant: Samsung Display Co., Ltd.

Inventor： Kyung Seop Kim ,  Byeong-Beom Kim ,  Joon Yong Park ,  Chang Oh Jeong ,  Hong Long Ning ,  Dong Min Lee

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L29/49 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L29/78693 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a semiconductor layer disposed on an insulation substrate; a gate electrode overlapping the semiconductor layer; a source electrode and a drain electrode overlapping the semiconductor layer; a first barrier layer disposed between the source electrode and the semiconductor layer; and a second barrier layer disposed between the drain electrode and the semiconductor layer, wherein the first barrier layer and the second barrier layer include nickel-chromium (NiCr).

Abstract translation: 薄膜晶体管阵列面板包括：设置在绝缘基板上的半导体层; 与半导体层重叠的栅电极; 与该半导体层重叠的源电极和漏电极; 设置在所述源电极和所述半导体层之间的第一阻挡层; 以及设置在所述漏电极和所述半导体层之间的第二阻挡层，其中所述第一阻挡层和所述第二阻挡层包括镍 - 铬（NiCr）。