公开(公告)号：US20240379635A1

公开(公告)日：2024-11-14

申请号：US18601335

申请日：2024-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin YIM ,  Jongkook KIM ,  Chengtar WU

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/28 ,  H01L23/498 ,  H01L25/00

Abstract: Provided a three-dimensional (3D) integrated circuit structure including a redistribution structure, a first semiconductor die on the redistribution structure, a substrate on the redistribution structure and adjacent to the first semiconductor die, a molding material on the redistribution structure and between the first semiconductor die and the substrate, an interconnection structure on the substrate and the first semiconductor die, the interconnection structure including a plurality of first bonding pads and a plurality of second bonding pads, and each second bonding pad of the second bonding pads being directly bonded to each first bonding pad of the first bonding pads, and a second semiconductor die on the interconnection structure.

公开(公告)号：US20250046721A1

公开(公告)日：2025-02-06

申请号：US18592004

申请日：2024-02-29

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Choongbin YIM ,  Jongkook KIM ,  Chengtar WU

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package includes a support substrate having a through hole and including an insulating layer, one or more wiring layers including a first wiring layer, and a first electronic device on the first wiring layer, a semiconductor chip positioned in the through hole to be at least partially surrounded by the support substrate and including a connection pad on a first surface of the semiconductor chip, an encapsulant filling at least a portion of the through hole and encapsulating at least a portion of the semiconductor chip, a first redistribution layer structure on the first surface of the semiconductor chip and including a first redistribution layer, and a second redistribution layer structure over a second surface of the semiconductor chip that is opposite to the first surface of the semiconductor chip, the second redistribution layer structure including a second redistribution layer.

公开(公告)号：US20240258222A1

公开(公告)日：2024-08-01

申请号：US18493234

申请日：2023-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chengtar WU ,  Jongkook KIM ,  Choongbin YIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/15311

Abstract: A 3D integrated circuit structure, comprising: a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of sacrificial pads on the redistribution layer structure; a plurality of conductive posts disposed adjacent the first semiconductor chip die, wherein the plurality of conductive posts is on the plurality of sacrificial pads, respectively; a molding material that is on the first semiconductor chip die, the plurality of sacrificial pads, the plurality of conductive posts, and the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure, wherein the second semiconductor chip die overlaps the first semiconductor chip die and the plurality of conductive posts in a vertical direction.

公开(公告)号：US20240258221A1

公开(公告)日：2024-08-01

申请号：US18493166

申请日：2023-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choongbin YIM ,  Jongkook KIM ,  Chengtar WU

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/16 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81

Abstract: A 3D integrated circuit structure includes a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of core balls on the redistribution layer structure and adjacent the first semiconductor chip die; a molding material encapsulating the first semiconductor chip die and the plurality of core balls on the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure. A footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.

公开(公告)号：US20240355802A1

公开(公告)日：2024-10-24

申请号：US18384912

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chengtar WU ,  Jongkook Kim

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/5381 ,  H01L23/5383 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L28/60 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204

Abstract: A three-dimensional integrated circuit structure includes: a first semiconductor die; and a second semiconductor die disposed on the first semiconductor die, wherein the first semiconductor die includes: a plurality of through-silicon vias (TSV); and a plurality of integrated stack capacitor (ISC) chips, wherein each of the plurality of ISC chips is disposed between adjacent through-silicon vias among the plurality of through-silicon vias.