公开(公告)号：US11551729B2

公开(公告)日：2023-01-10

申请号：US17215914

申请日：2021-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangyun Kim ,  Kyungryun Kim ,  Junghwan Park ,  Yeonkyu Choi

IPC: G11C11/34 ,  G11C5/14 ,  G11C7/22 ,  G11C7/06

Abstract: A memory device includes: a first circuit; a second circuit; and an adaptive body bias generator configured to receive frequency detection information or temperature detection information, to apply a first forward body bias or a first reverse body bias to the first circuit in response to the frequency detection information or the temperature detection information, and to apply a second forward body bias or a second reverse body bias to the second circuit in response to the frequency detection information or the temperature detection information.

公开(公告)号：US12040046B2

公开(公告)日：2024-07-16

申请号：US18447950

申请日：2023-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Hoon Jang ,  Kyungryun Kim ,  Young Ju Kim ,  Seung-Jun Lee ,  Youngbin Lee ,  Yeonkyu Choi

IPC: G11C8/18 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1093

Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.

公开(公告)号：US11545196B2

公开(公告)日：2023-01-03

申请号：US17466754

申请日：2021-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbin Lee ,  Kiho Kim ,  Jinhoon Jang ,  Yeonkyu Choi

IPC: G11C7/10 ,  G11C7/14

Abstract: Provided are an apparatus, a memory device, and a method for storing a plurality of parameter codes for an operation parameter. The memory device includes a mode register and a control logic circuit. To set a first operating condition and a second operating condition for one operation parameter, the mode register stores a first parameter code for the operation parameter and a second parameter code, which is expressed as an offset value from the first parameter code. The control logic circuit sets the first operating condition as a current operating condition of the memory device by using the first parameter code based on a first control code and sets the second operating condition as the current operating condition of the memory device by using the first parameter code and the second parameter code based on a second control code.

公开(公告)号：US10304547B2

公开(公告)日：2019-05-28

申请号：US15700324

申请日：2017-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonkyu Choi ,  Seungjun Shin

IPC: H01L27/115 ,  G11C16/32 ,  G11C7/22 ,  G11C29/02

Abstract: A training method for a memory device includes providing, at a memory controller, a clock signal to the memory device to synchronize a control signal at a reference time point of the clock signal. When the clock signal, such as a training clock signal, does not transition after the reference time point, a failure time point is found at which the memory device fails to sample the control signal at the reference time point, based on the clock signal and the control signal. A synchronization time point of the control signal may be set, at which the memory device secures a sampling margin for sampling the control signal at the reference time point, based on the failure time point. A sampler circuit may sample the control signal at an edge of a rising edge of the clock signal.

公开(公告)号：US11804254B2

公开(公告)日：2023-10-31

申请号：US17529900

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saemi Song ,  Dokyun Kim ,  Yeonkyu Choi ,  Doohee Hwang

IPC: G11C11/406

CPC classification number: G11C11/40626 ,  G11C11/40615 ,  G11C11/40622

Abstract: Provided are a memory device and a method of refreshing the memory device regardless of a refresh rate multiplier for a temperature. In response to a refresh command at each base refresh rate (tREFi) based on a measured temperature, a memory device refreshes M memory cell rows at room temperature, refreshes 2M memory cell rows at a high temperature, and refreshes (½)M memory cell rows at a low temperature. The memory device refreshes (n+1)*M memory cell rows at a base refresh rate tREFi in response to a refresh command applied after n skipped base refresh rates, and refreshes (n+1)*M memory cell rows at a base refresh rate tREFi in response to a pulling-in refresh command.

公开(公告)号：US20180122486A1

公开(公告)日：2018-05-03

申请号：US15700324

申请日：2017-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonkyu Choi ,  Seungjun Shin

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2245 ,  G11C2207/2254 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A training method for a memory device includes providing, at a memory controller, a clock signal to the memory device to synchronize a control signal at a reference time point of the clock signal. When the clock signal, such as a training clock signal, does not transition after the reference time point, a failure time point is found at which the memory device fails to sample the control signal at the reference time point, based on the clock signal and the control signal. A synchronization time point of the control signal may be set, at which the memory device secures a sampling margin for sampling the control signal at the reference time point, based on the failure time point. A sampler circuit may sample the control signal at an edge of a rising edge of the clock signal.

公开(公告)号：US11783880B2

公开(公告)日：2023-10-10

申请号：US17496003

申请日：2021-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Hoon Jang ,  Kyungryun Kim ,  Young Ju Kim ,  Seung-Jun Lee ,  Youngbin Lee ,  Yeonkyu Choi

IPC: G11C8/18 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/1093

Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.

公开(公告)号：US11688438B2

公开(公告)日：2023-06-27

申请号：US18071054

申请日：2022-11-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngbin Lee ,  Kiho Kim ,  Jinhoon Jang ,  Yeonkyu Choi

IPC: G11C7/10 ,  G11C7/14

CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1045 ,  G11C7/14

Abstract: Provided are an apparatus, a memory device, and a method for storing a plurality of parameter codes for an operation parameter. The memory device includes a mode register and a control logic circuit. To set a first operating condition and a second operating condition for one operation parameter, the mode register stores a first parameter code for the operation parameter and a second parameter code, which is expressed as an offset value from the first parameter code. The control logic circuit sets the first operating condition as a current operating condition of the memory device by using the first parameter code based on a first control code and sets the second operating condition as the current operating condition of the memory device by using the first parameter code and the second parameter code based on a second control code.

公开(公告)号：US11508429B2

公开(公告)日：2022-11-22

申请号：US17399402

申请日：2021-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonkyu Choi ,  Dokyun Kim ,  Seongjin Lee ,  Doohee Hwang

IPC: G11C11/406 ,  G11C7/10

Abstract: A memory system includes a memory controller and a memory device. The memory controller generates refresh commands periodically by an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during a refresh cycle time. The memory device includes a memory cell array including memory cells connected to a plurality of wordlines, a temperature sensor configured to provide temperature information by measuring an operation temperature of the memory cell array and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller varies a hammer ratio of a unit hammer execution number of the hammer refresh operation executed during the refresh cycle time with respect to a unit normal execution number of the normal refresh operation executed during the refresh cycle time.