公开(公告)号：US20250132249A1

公开(公告)日：2025-04-24

申请号：US18761886

申请日：2024-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Muryeong KUK ,  Dosun LEE ,  Seongheum CHOI ,  Hongkeun PARK ,  Giwoong SHIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An interconnection structure may include a first insulating interlayer on a substrate, a first metal pattern on the substrate and passing through the first insulating interlayer, a seed metal layer pattern surrounding a portion of a sidewall of the first metal pattern and a bottom of the first metal pattern, and a second metal pattern. The second metal pattern may directly contact an uppermost surface of the seed metal layer pattern, the upper sidewall of the first metal pattern, and the upper surface of the first metal pattern. An upper sidewall and an upper surface of the first metal pattern may be exposed by the seed metal layer pattern. The second metal pattern may fill at least a recess between the first insulating interlayer and the first metal pattern.

公开(公告)号：US20240170546A1

公开(公告)日：2024-05-23

申请号：US18216640

申请日：2023-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seongheum CHOI ,  Chunghwan SHIN ,  Rakhwan Kim ,  Yeji Song

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/41791 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/66795

Abstract: A semiconductor device includes: an active fin disposed on a substrate and protruding from an upper surface of the substrate; a gate structure disposed on the active fin; a source/drain layer disposed on a portion of the active fin adjacent to the gate structure; an ohmic contact pattern on the source/drain layer; and a contact plug disposed on an upper surface of the ohmic contact pattern, wherein the contact plug includes: a conductive structure including a metal; and a barrier pattern covering a lower surface and a sidewall of the conductive structure, wherein a thickness of the barrier pattern is equal to or less than about 10 Å, and wherein a maximum diameter of a grain of the metal included in the conductive structure is in a range of about 8 nn to about 15 nm.