公开(公告)号：US20210057411A1

公开(公告)日：2021-02-25

申请号：US16864260

申请日：2020-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung KIM ,  Jinwoo JEONG ,  Jiwook KWON ,  Raheel AZMAT ,  Kwanyoung CHUN

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

公开(公告)号：US20160027703A1

公开(公告)日：2016-01-28

申请号：US14807220

申请日：2015-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho DO ,  Sanghoon BAEK ,  Sang-Kyu OH ,  Kwanyoung CHUN ,  Sunyoung PARK ,  Taejoong SONG

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L27/0207 ,  H01L27/092

Abstract: Provided is a method of fabricating a semiconductor device with a field effect transistor. The method may include forming a first gate electrode and a second gate electrode extending substantially parallel to each other and each crossing a PMOSFET region on a substrate and an NMOSFET region on the substrate; forming an interlayered insulating layer covering the first gate electrode and the second gate electrode; patterning the interlayered insulating layer to form a first sub contact hole on the first gate electrode, the first sub contact hole being positioned between the PMOSFET region and the NMOSFET region, when viewed in a plan view; and patterning the interlayered insulating layer to form a first gate contact hole and to expose a top surface of the second gate electrode, wherein the first sub contact hole and the first gate contact hole form a single communication hole.

Abstract translation: 提供一种制造具有场效应晶体管的半导体器件的方法。 该方法可以包括形成基本上彼此平行延伸并且每个跨越衬底上的PMOSFET区域和衬底上的NMOSFET区域延伸的第一栅电极和第二栅电极; 形成覆盖所述第一栅电极和所述第二栅电极的层间绝缘层; 在第一栅电极上图形化层间绝缘层以形成第一子接触孔，当在平面图中观察时，第一子接触孔位于PMOSFET区和NMOSFET区之间; 以及图案化所述层间绝缘层以形成第一栅极接触孔并暴露所述第二栅电极的顶表面，其中所述第一子接触孔和所述第一栅极接触孔形成单个连通孔。

公开(公告)号：US20150084097A1

公开(公告)日：2015-03-26

申请号：US14312702

申请日：2014-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyeon JEON ,  Rwik SENGUPTA ,  Chulhong PARK ,  Kwanyoung CHUN ,  Yusun LEE ,  Hyun-Jong LEE

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11861 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction.

Abstract translation: 半导体器件包括其上设置有多个逻辑单元的基板和设置在基板上并沿第一方向延伸的多个有源部分。 触点和栅极结构在与第一方向相交的第二方向上延伸并且交替地布置。 公共导线沿第一方向沿多个逻辑单元的边界区域延伸。 至少一个触点通过它们之间的通孔电连接到公共导线，并且每个触点与多个有源部分相交。 触点的端部沿着第一方向彼此对准。

公开(公告)号：US20250072106A1

公开(公告)日：2025-02-27

申请号：US18435305

申请日：2024-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo PARK ,  Byungju KANG ,  Jaehyoung LIM ,  Kwanyoung CHUN ,  Subin CHOI

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A three-dimensional semiconductor device may include a back-side metal layer, a lower channel pattern on the back-side metal layer, first and second lower source/drain patterns, which are spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern being connected to the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern being connected to the upper channel pattern, a second upper source/drain pattern on the second lower source/drain pattern, and a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern. The wide via may include first and second via portions having first and second top surfaces, and here, the second top surface may be located at a level lower than the first top surface.

公开(公告)号：US20230268336A1

公开(公告)日：2023-08-24

申请号：US18140115

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungkyu CHAE ,  Kwanyoung CHUN ,  Yoonjin KIM

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.

公开(公告)号：US20230022952A1

公开(公告)日：2023-01-26

申请号：US17960277

申请日：2022-10-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyung KIM ,  Kwanyoung CHUN ,  Yoonjin KIM

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02 ,  H01L29/786

Abstract: Disclosed is a semiconductor device comprising an active region that protrudes upwardly from a substrate, a plurality of channel patterns that are spaced apart from each other in a first direction on the active region, and a gate electrode that extends in the first direction on the active region and covers the plurality of channel patterns. Each of the plurality of channel patterns includes a plurality of semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the active region. The gate electrode covers the top surface of the active region between the plurality of channel patterns.

公开(公告)号：US20230136881A1

公开(公告)日：2023-05-04

申请号：US17891760

申请日：2022-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Panjae PARK ,  Yoonjin KIM ,  Kwanyoung CHUN

IPC: G06F30/392 ,  H01L23/528 ,  G06F30/394

Abstract: A cell including individual source regions includes active regions extending in a first direction and being spaced apart from each other in a second direction different from the first direction, gate lines extending across the active regions in the second direction and being spaced apart from each other in the first direction, first contacts arranged on both sides of each of the gate lines in the first direction and connected to the active regions, metal lines arranged over the gate lines and the first contacts, the metal lines extending in the first direction and being spaced apart from each other in the second direction, second contacts connecting the gate lines to the metal lines, and vias connecting the first contacts to the metal lines.

公开(公告)号：US20220384415A1

公开(公告)日：2022-12-01

申请号：US17527432

申请日：2021-11-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Panjae PARK ,  Byungju KANG ,  Yoonjeong KIM ,  Kwanyoung CHUN

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L29/08

Abstract: An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.

公开(公告)号：US20220271034A1

公开(公告)日：2022-08-25

申请号：US17740900

申请日：2022-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyung KIM ,  Jinwoo JEONG ,  Jiwook KWON ,  Raheel AZMAT ,  Kwanyoung CHUN

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/02

Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

公开(公告)号：US20210151426A1

公开(公告)日：2021-05-20

申请号：US16931585

申请日：2020-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungkyu CHAE ,  Kwanyoung CHUN ,  Yoonjin KIM

IPC: H01L27/02

Abstract: A semiconductor device includes a pair of first and second dummy active regions extending in a first horizontal direction and spaced apart from each other in a second horizontal direction; a pair of first and second circuit active regions extending in the first horizontal direction and spaced apart in the second horizontal direction; and a plurality of line patterns extending in the second horizontal direction and spaced apart in the first horizontal direction. The pair of first and second dummy active regions may be between a pair of line patterns adjacent to each other among the plurality of line patterns. At least one of the first and second dummy active regions may have a width-changing portion in which a width of the at least one of the first and second dummy active regions changes in the second horizontal direction between the pair of line patterns adjacent to each other.