公开(公告)号：US20130248990A1

公开(公告)日：2013-09-26

申请号：US13718138

申请日：2012-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-Jun KIM ,  Hae-Wang LEE ,  Chul-Hong PARK ,  Dong-Kyun SOHN ,  Jong-Shik YOON

IPC: H01L23/538 ,  H01L29/78

CPC classification number: H01L23/5384 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/5283 ,  H01L23/53238 ,  H01L23/53266 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.

Abstract translation: 半导体器件及其制造方法包括在衬底上的层间电介质膜图案，层间电介质膜图案内的第一布线，并且具有第一方向的第一长度，层间电介质膜图案内的第二布线和 与第一布线分离，以及与第一布线和第二布线接触的间隔件。 间隔件将第一布线和第二布线彼此电分离。 第二布线具有与第一方向上的第一长度不同的第二长度。

公开(公告)号：US20190123140A1

公开(公告)日：2019-04-25

申请号：US16051667

申请日：2018-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pan-Jae Park ,  Jae-Seok Yang ,  Young-Hun KIM ,  Hae-Wang LEE ,  Kwan-Young CHUN

IPC: H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L27/02 ,  H01L29/78

Abstract: A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.