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公开(公告)号：US20170257136A1
公开(公告)日：2017-09-07
申请号：US15062025
申请日：2016-03-04
Applicant: RAYTHEON COMPANY
Inventor： John P Gianvittorio , Denpol Kultran , Harry Marr
Abstract: A reconfigurable discrete time analog signal processor includes a finite impulse response (FIR) filter configured to receive a portion of an RF transmit signal, to receive FIR coefficients, and to generate a leakage cancellation signal based on the portion of the RF transmit signal and the FIR coefficients, the FIR filter including sample and hold (SH) circuits configured to receive the portion of the RF transmit signal, to sample the portion of the RF transmit signal at successive sample times according to a sample clock, and to generate sampled analog voltage signals, and analog multipliers coupled to the SH circuits and configured to multiply the sampled analog voltage signals by binary multiplication factors to generate the leakage cancellation signal.
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公开(公告)号：US10200075B2
公开(公告)日：2019-02-05
申请号：US15062025
申请日：2016-03-04
Applicant: RAYTHEON COMPANY
Inventor： John P Gianvittorio , Denpol Kultran , Harry Marr
Abstract: A reconfigurable discrete time analog signal processor includes a finite impulse response (FIR) filter configured to receive a portion of an RF transmit signal, to receive FIR coefficients, and to generate a leakage cancellation signal based on the portion of the RF transmit signal and the FIR coefficients, the FIR filter including sample and hold (SH) circuits configured to receive the portion of the RF transmit signal, to sample the portion of the RF transmit signal at successive sample times according to a sample clock, and to generate sampled analog voltage signals, and analog multipliers coupled to the SH circuits and configured to multiply the sampled analog voltage signals by binary multiplication factors to generate the leakage cancellation signal.
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公开(公告)号：US09923549B2
公开(公告)日：2018-03-20
申请号：US14849524
申请日：2015-09-09
Applicant: Raytheon Company
Inventor： Denpol Kultran , Richard T. Hennegan , Harry B. Marr
Abstract: There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.
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公开(公告)号：US09703991B2
公开(公告)日：2017-07-11
申请号：US14849529
申请日：2015-09-09
Applicant: Raytheon Company
Inventor： Denpol Kultran , Won Chon , Harry B. Marr
Abstract: There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.
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Patent Agency Ranking
5.发明授权High speed, high efficiency, high power RF pulse modulating integrated switch 有权高速，高效率，高功率射频脉冲调制集成开关公开(公告)号：US09287870B2
公开(公告)日：2016-03-15
申请号：US14075407
申请日：2013-11-08
Applicant: Raytheon Company
Inventor： Mark T. Richardson , Denpol Kultran , George W. Gerace , Richard D. Young , Mark E. Stading , Jeffrey H. Saunders
CPC classification number: H03K19/01721 , G01S7/02 , G01S7/282 , G01S13/02 , H03K19/0013
Abstract: Embodiments of a drain modulator that uses high power switch sensing to control active pulldown are generally described herein. In some embodiments, a logic and sense module is arranged to receive a control signal for controlling an on and an off state of an input of a switch to turn a high power voltage at an output of the switch on and off. A pullup module and a pulldown module are coupled to the input of the switch. An active pulldown module coupled to the output of the switch. The logic and sense module monitors the input to the switch and activates the active pulldown module to drain the output of the switch to a zero voltage when the input of the switch transitions to the off state.
Abstract translation: 在此通常描述使用高功率开关感测来控制有源下拉的漏极调制器的实施例。 在一些实施例中，逻辑和感测模块被布置成接收用于控制开关输入的导通和关断状态的控制信号，以在开关的输出端接通和断开电源。 上拉模块和下拉模块耦合到开关的输入端。 耦合到开关的输出的主动下拉模块。 逻辑和感测模块监控开关的输入，并激活有源下拉模块，当开关的输入转换到关闭状态时，将开关的输出消耗到零电压。
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6.发明申请HIGH SPEED, HIGH EFFICIENCY, HIGH POWER RF PULSE MODULATING INTEGRATED SWITCH 有权高速，高效，高功率RF脉冲调制集成开关公开(公告)号：US20150130657A1
公开(公告)日：2015-05-14
申请号：US14075407
申请日：2013-11-08
Applicant: Raytheon Company
Inventor： Mark T. Richardson , Denpol Kultran , George W. Gerace , Richard D. Young , Mark E. Stading , Jeffrey H. Saunders
IPC: H03K19/017 , G01S7/02 , G01S13/02 , H03K19/00
CPC classification number: H03K19/01721 , G01S7/02 , G01S7/282 , G01S13/02 , H03K19/0013
Abstract: Embodiments of a drain modulator that uses high power switch sensing to control active pulldown are generally described herein. In some embodiments, a logic and sense module is arranged to receive a control signal for controlling an on and an off state of an input of a switch to turn a high power voltage at an output of the switch on and off. A pullup module and a pulldown module are coupled to the input of the switch. An active pulldown module coupled to the output of the switch. The logic and sense module monitors the input to the switch and activates the active pulldown module to drain the output of the switch to a zero voltage when the input of the switch transitions to the off state.
Abstract translation: 在此通常描述使用高功率开关感测来控制有源下拉的漏极调制器的实施例。 在一些实施例中，逻辑和感测模块被布置成接收用于控制开关输入的导通和关断状态的控制信号，以在开关的输出端接通和断开电源。 上拉模块和下拉模块耦合到开关的输入端。 耦合到开关的输出的主动下拉模块。 逻辑和感测模块监控开关的输入，并激活有源下拉模块，当开关的输入转换到关闭状态时，将开关的输出消耗到零电压。
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公开(公告)号：US09626533B2
公开(公告)日：2017-04-18
申请号：US14849529
申请日：2015-09-09
Applicant: Raytheon Company
Inventor： Denpol Kultran , Won Chon , Harry B. Marr
Abstract: There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.
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公开(公告)号：US20170070212A1
公开(公告)日：2017-03-09
申请号：US14849524
申请日：2015-09-09
Applicant: Raytheon Company
Inventor： Denpol Kultran , Richard T. Hennegan , Harry B. Marr
Abstract: There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.
Abstract translation: 提供了用于对输入电压信号进行滤波以产生输出电流信号的有限脉冲响应（FIR）滤波器，FIR滤波器包括被配置为同时接收输入电压信号的多个采样和保持（SH）电路，以对 输入电压信号，根据采样时钟连续采样时间，并产生多个采样电压信号;以及多个可编程模拟乘法器，耦合到多个SH电路，并被配置为将多个采样电压信号乘以多个 的二进制乘法因子来产生输出电流信号。
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公开(公告)号：US20170070210A1
公开(公告)日：2017-03-09
申请号：US14849529
申请日：2015-09-09
Applicant: Raytheon Company
Inventor： Denpol Kultran , Won Chon , Harry B. Marr
IPC: H03H15/00
Abstract: There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.
Abstract translation: 提供了一种用于将输入电压信号乘以二进制系数的可编程乘法器电路，所述乘法器电路包括跨导体，其包括被配置为将输入电压信号转换为电流信号的第一放大晶体管，所述第一放大晶体管具有被配置为 接收所述输入电压信号，以及系数乘法器，耦合到所述跨导体并且被配置为将所述电流信号乘以所述二进制系数以产生放大的电流信号。
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