公开(公告)号：US11907149B2

公开(公告)日：2024-02-20

申请号：US17116454

申请日：2020-12-09

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Yiftach Benjamini

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F13/4213 ,  G06F13/4226 ,  G06F2213/0042

Abstract: Sideband signaling in Universal Serial Bus (USB) Type-C communication link allows multiple protocols that are tunneled through a USB link, where sideband signals may be provided through the sideband use (SBU) pins. Further, the SBU pins may be transitioned between different modes of sideband signals. In particular, signals in an initial mode may indicate a need or desire transition to a second mode. After a negotiation, linked devices agree to transition, the two devices may transition to the second mode. By providing this inband sideband signaling that allows mode changes, more protocols can be tunneled with accompanying sideband signaling and flexibility of the USB link is expanded.

公开(公告)号：US11064295B2

公开(公告)日：2021-07-13

申请号：US16597902

申请日：2019-10-10

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Yiftach Benjamini ,  Sharon Graif

IPC: H04R3/00 ,  G06F3/16 ,  H04R3/04 ,  G10L21/0208 ,  H04L29/06 ,  G06F9/30

Abstract: Systems and methods for scrambling data-port audio in SOUNDWIRE™ systems include a scramble enable feature that allows a data source to scramble an outgoing channel content with a cyclic linear feedback shift register (LFSR) using a pseudo-random binary sequence (PRBS) such as, but not limited to, the PRBS defined in the SOUNDWIRE specification. Data ports for audio sinks receiving the scrambled content descramble the content for use by the audio sink. In a specific exemplary aspect, an output of the LFSR is added or subtracted with the audio data to make the microphones independent of one another and reduce crosstalk.

公开(公告)号：US10795400B2

公开(公告)日：2020-10-06

申请号：US15966077

申请日：2018-04-30

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/12 ,  G06F13/42

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

公开(公告)号：US20220179814A1

公开(公告)日：2022-06-09

申请号：US17116454

申请日：2020-12-09

Applicant: QUALCOMM Incorporated

Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Yiftach Benjamini

IPC: G06F13/38 ,  G06F13/42

Abstract: Sideband signaling in Universal Serial Bus (USB) Type-C communication link allows multiple protocols that are tunneled through a USB link, where sideband signals may be provided through the sideband use (SBU) pins. Further, the SBU pins may be transitioned between different modes of sideband signals. In particular, signals in an initial mode may indicate a need or desire transition to a second mode. After a negotiation, linked devices agree to transition, the two devices may transition to the second mode. By providing this inband sideband signaling that allows mode changes, more protocols can be tunneled with accompanying sideband signaling and flexibility of the USB link is expanded.

公开(公告)号：US11287842B2

公开(公告)日：2022-03-29

申请号：US16927657

申请日：2020-07-13

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/12 ,  G06F13/42

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

公开(公告)号：US20200153593A1

公开(公告)日：2020-05-14

申请号：US16186961

申请日：2018-11-12

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Shaul Yohai Yifrach ,  Lior Amarilio

IPC: H04L5/00 ,  G06F13/42 ,  H04L29/08 ,  H04L12/823 ,  H04L12/861

Abstract: Systems and methods for reducing latency on long distance point-to-point links where the point-to-point link is a Peripheral Component Interconnect (PCI) express (PCIE) link that modifies a receiver to advertise infinite or unlimited credits. A transmitter sends packets to the receiver. If the receiver's buffers fill, the receiver, contrary to PCIE doctrine, drops the packet and returns a negative acknowledgement (NAK) packet to the transmitter. The transmitter, on receipt of the NAK packet, resends packets beginning with the one for which the NAK packet was sent. By the time these resent packets arrive, the receiver will have had time to manage the packets in the buffers and be ready to receive the resent packets.

公开(公告)号：US20200019523A1

公开(公告)日：2020-01-16

申请号：US16032238

申请日：2018-07-11

Applicant: QUALCOMM Incorporated

Inventor： Lior Amarilio ,  Sharon Graif ,  Yiftach Benjamini

IPC: G06F13/362 ,  G06F3/16 ,  G06F13/40

Abstract: Delayed bank switch commands in an audio system such as a SOUNDWIRE audio system may have slaves that have had a delay register added to register banks for each data port. When a bank switch command is received, a slave consults the delay register and delays switching by a number of frames indicated in the delay register. Such delays may be used to prevent interpreting non-audio data as part of a data stream, particularly at start up and closure of audio streams. If an audio stream is active, the delay may be set to zero. By precluding the evaluation of non-audio data, audio artifacts may be avoided and a better user experience provided.

公开(公告)号：US20220129398A1

公开(公告)日：2022-04-28

申请号：US17082873

申请日：2020-10-28

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Lior Amarilio ,  Sharon Graif

IPC: G06F13/20 ,  G06F13/42

Abstract: Tunneling over Universal Serial Bus (USB) sideband channel systems and methods provide a way to tunnel I2C transactions between a master and slaves over USB 4.0 sideband channels. More particularly, a slave address table lookup (SATL) circuit is added to a host circuit. Signals from an I2C bus are received at the host, and any address associated with a destination is translated by the SATL. The translated address is passed to a low-speed interface associated with a sideband channel in the host circuit. Signals received at the low-speed interface are likewise reverse translated in the SATL and then sent out through the I2C bus. In this fashion, low-speed I2C signals may be routed over the sideband channel through the low-speed sideband interface portion of the USB interface.

公开(公告)号：US20200341506A1

公开(公告)日：2020-10-29

申请号：US16927657

申请日：2020-07-13

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Amit Gil ,  Shaul Yohai Yifrach

IPC: G06F1/12 ,  G06F13/42

Abstract: Systems and methods for time synchronization for clocks separated by a communication link allow a master clock to be positioned at a downstream-facing port or an upstream-facing port and to send synchronization commands with an associated time stamp embedded in transport layer protocol (TLP) prefixes to a slave clock. The slave clock may update its time value based on the received time stamp. Further, the slave may calculate a round trip delay between the master clock and the slave clock and use this delay calculation to correct the slave clock. The delay calculation may likewise be made using TLP prefixes. By using TLP prefixes in this fashion, the time synchronization can piggyback on existing message traffic, which reduces signaling overhead. Likewise, by using the TLP prefixes, the time synchronization may be initiated from either an upstream-facing port or a downstream-facing port.

公开(公告)号：US20200089645A1

公开(公告)日：2020-03-19

申请号：US16569816

申请日：2019-09-13

Applicant: QUALCOMM Incorporated

Inventor： Yiftach Benjamini ,  Lior Amarilio ,  Amit Gil ,  James Lionel Panian ,  Dafna Shaool

IPC: G06F13/42 ,  H04L9/08

Abstract: Security techniques for a Peripheral Component Interconnect (PCI) express (PCIE) system include a transport layer protocol (TLP) packet that has a prepended TLP prefix indicating the security features of the TLP packet and an integrity check value (ICV) appended to the TLP packet. The ICV is based on the TLP packet and any TLP prefixes including a security prefix. At a receiver, if the ICV does not match, then the receiver has evidence that the TLP packet may have been subjected to tampering. Further, the TLP packet may be encrypted to prevent snooping, and this feature would be indicated in the TLP prefix. Still further, the TLP prefix may include a counter that may be used to prevent replay attacks. PCIE contemplates flexible TLP prefixes, and thus, the standard readily accommodates the addition of a TLP prefix which indicates the security features of the TLP packet.