公开(公告)号：US20220392867A1

公开(公告)日：2022-12-08

申请号：US17339830

申请日：2021-06-04

申请人： QUALCOMM Incorporated

发明人： Li-Sheng WENG ,  Charles David PAYNTER ,  Ryan LANE ,  Jianwen XU ,  William STONE

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

摘要： A package comprising a first integrated device comprising a plurality of first pillar interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a metallization portion located over the first integrated device and the encapsulation layer, wherein the metallization portion includes at least one passivation layer and a plurality of metallization layer interconnects, wherein the plurality of first pillar interconnects is coupled to the plurality of metallization layer interconnects; and a second integrated device comprising a plurality of second pillar interconnects, wherein the second integrated device is coupled to the plurality of metallization layer interconnects through a plurality of second pillar interconnects and a plurality of solder interconnects.

公开(公告)号：US20240071993A1

公开(公告)日：2024-02-29

申请号：US17894057

申请日：2022-08-23

申请人： QUALCOMM Incorporated

发明人： Yanmei SONG ,  William STONE ,  Jianwen XU ,  John HOLMES ,  Ryan LANE

IPC分类号： H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC分类号： H01L25/0652 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L2224/16235

摘要： A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion, a second integrated device coupled to the first metallization portion, a second metallization portion coupled to the first metallization portion through a first plurality of pillar interconnects, a first chiplet located between the first metallization portion and the second metallization portion, wherein the first chiplet is configured to be electrically coupled to the first integrated device through the first metallization portion, and a second chiplet located between the first metallization portion and the second metallization portion, wherein the second chiplet is configured to be electrically coupled to the second integrated device through the first metallization portion.

公开(公告)号：US20240072032A1

公开(公告)日：2024-02-29

申请号：US17894043

申请日：2022-08-23

申请人： QUALCOMM Incorporated

发明人： Yanmei SONG ,  William STONE ,  Jianwen XU ,  Senthil SIVASWAMY ,  John HOLMES ,  Ryan LANE

IPC分类号： H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L25/50 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/82 ,  H01L24/92 ,  H01L24/95 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/016 ,  H01L2224/0557 ,  H01L2224/16145 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/224 ,  H01L2224/24155 ,  H01L2224/73209 ,  H01L2224/81815 ,  H01L2224/821 ,  H01L2224/92124 ,  H01L2225/06513 ,  H01L2225/06524

摘要： A package comprising a first metallization portion, a first integrated device coupled to the first metallization portion through a first plurality of pillar interconnects, and a first chiplet located between the first integrated device and the first metallization portion. The first chiplet is coupled to the first integrated device through a first plurality of inter pillar interconnects. The first chiplet may include an active chiplet. The first chiplet may include a passive chiplet.

公开(公告)号：US20150318229A1

公开(公告)日：2015-11-05

申请号：US14702276

申请日：2015-05-01

申请人： QUALCOMM Incorporated

发明人： Jianwen XU ,  Lizabeth Ann KESER ,  William STONE ,  Steve Joseph BEZUK ,  Nicholas Ka Ming YU

IPC分类号： H01L23/31 ,  H01L23/532 ,  H01L23/498 ,  H01L23/528

CPC分类号： H01L23/3114 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/525 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/5329 ,  H01L29/0657 ,  H01L2224/11

摘要： A wafer level package device may include a molding compound that encapsulates a substrate, a back end of line and front end of line layer on the substrate and a passivation layer of a redistribution layer without encapsulating a metal layer on the passivation layer.

摘要翻译： 晶片级封装器件可以包括封装衬底，衬底的后端和衬底上的线层前端的模制化合物以及再分配层的钝化层，而不在钝化层上封装金属层。