公开(公告)号：US20250098301A1

公开(公告)日：2025-03-20

申请号：US18469483

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Deepak SHARMA ,  Yan SUN ,  Shreesh NARASIMHA

IPC: H01L27/12 ,  H01L21/768 ,  H01L23/528 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are gate-tie-down (GTD) cells that utilize a backside power delivery scheme, where metal wires that deliver power are provided on the back of the wafer. As a result, ultra-low height standard cell can be enabled. Also higher area scaling may be achieved. Further, performance and power gain can be maximized.

公开(公告)号：US20250098220A1

公开(公告)日：2025-03-20

申请号：US18470207

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are complementary field effect transistor (CFET) circuits with vertical routing structures and methods for making the same. In an aspect, a semiconductor structure comprises: a first FET comprising a first source/drain (S/D) region, a second S/D region, and a first gate; a second FET disposed above the first FET and comprising a third S/D region, a fourth S/D region, and a second gate; a frontside metal (FM) layer disposed above the second FET and comprising a set of FM conductors extending in an X direction; and a backside metal (BM) layer disposed below the first FET and comprising a set of BM conductors extending in the X direction. The semiconductor structure also comprises a vertical connector, extending in a Z direction, that electrically couples one of the set of BM conductors to the third S/D region, the fourth S/D region, or the second gate.

公开(公告)号：US20250098204A1

公开(公告)日：2025-03-20

申请号：US18469489

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Deepak SHARMA ,  Yan SUN ,  Shreesh NARASIMHA

IPC: H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66

Abstract: Disclosed are gate-tie-down (GTD) cells that utilize a backside power delivery scheme, where metal wires that deliver power are provided on the back of the die. The backside power may be delivered to the gates through S/Ds and through frontside contacts. As a result, ultra-low height standard cell can be enabled. Also higher area scaling may be achieved. Further, performance and power gain can be maximized.

公开(公告)号：US20240429236A1

公开(公告)日：2024-12-26

申请号：US18339715

申请日：2023-06-22

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Peijie FENG

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Disclosed are gate-all-around (GAA) devices formed on a nanosheet wafer that includes multiple nanosheet (NS) structures including first and second NS structures. The first NS structure may include N nanosheets, where N≥2. All N nanosheets may function as channels in the first NS structure. The second NS structure may include one or more nanosheets in which N−M of them function as channels, where 1≤M

公开(公告)号：US20250151386A1

公开(公告)日：2025-05-08

申请号：US18503839

申请日：2023-11-07

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Disclosed are complementary field effect transistor (CFET) circuits with direct vertical connectors and methods for making the same. In an aspect, a semiconductor structure comprises a first field effect transistor (FET) of a first charge carrier type, comprising first and second source/drain (S/D) regions and one or more channels that electrically connect the first and second S/D regions through a first gate structure; a second FET of a second charge carrier type, disposed above the first FET in a Z direction and comprising third and fourth S/D regions and one or more channels that electrically connect the third and fourth S/D regions through a second gate structure; and a vertical connector extending in the Z direction from a top surface of the first S/D region to a bottom surface of the third S/D region and electrically coupling the first S/D region to the third No errors found.S/D region.

公开(公告)号：US20250098221A1

公开(公告)日：2025-03-20

申请号：US18470226

申请日：2023-09-19

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

Abstract: Disclosed are complementary field effect transistor (CFET) circuits with vertical routing structures and methods for making the same. In an aspect, a semiconductor structure comprises a first field effect transistor (FET) of a first charge carrier type, comprising a first source/drain (S/D) region, a second S/D region, and a first gate; a second FET of a second charge carrier type, disposed above the first FET and comprising a third S/D region, a fourth S/D region, and a second gate; a frontside metal (FM) layer disposed above the second FET and comprising an FM conductor extending in an X direction; a backside metal (BM) layer disposed below the first FET and comprising a BM conductor extending in the X direction; and a vertical connector extending in the Z direction, that electrically couples the BM conductor to the FM conductor.

公开(公告)号：US20250151253A1

公开(公告)日：2025-05-08

申请号：US18503776

申请日：2023-11-07

Applicant: QUALCOMM Incorporated

Inventor： Yan SUN ,  Shreesh NARASIMHA

IPC: H10B10/00 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: In an aspect, a semiconductor memory cell comprises a first inverter comprising a top field effect transistor (FET) and a bottom FET in a first complementary FET (CFET) structure having a first common gate as an input node of the first inverter, and a second inverter comprising a top FET and a bottom FET in a second complementary CFET structure having a second common gate as an input node of the second inverter. The first and second inverters are cross-coupled to each other using backside metal (BM) structures. The top and bottom FETs may be N-type and P-type, respectively, or vice-versa. The memory cell may include a passgate using top FETs of two additional CFET structures with bottom FETs disabled, or vice versa. The disabled FETs may be disabled during wafer process by suppressing growth of source/drain epitaxial regions and/or by removal of channels through etching and dielectric fill.

公开(公告)号：US20250098256A1

公开(公告)日：2025-03-20

申请号：US18469465

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Yan SUN ,  Shreesh NARASIMHA

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate stack extending along a first direction in a front portion of the semiconductor structure, the gate stack including a first gate structure; a first channel structure disposed through the first gate structure and extending along a second direction; a first source/drain (S/D) structure adjacent the first gate structure and electrically coupled to the first channel structure; a backside dielectric layer disposed in a back portion of the semiconductor structure opposing the front portion; and a backside conductive structure in contact with the first S/D structure and disposed at least partially in the back portion of the semiconductor structure and through the backside dielectric layer. The backside conductive structure has a length in the first direction greater than a width of the first channel structure in the first direction.

公开(公告)号：US20250098217A1

公开(公告)日：2025-03-20

申请号：US18469496

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Yan SUN ,  Shreesh NARASIMHA ,  Deepak SHARMA

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A field effect transistor (FET) structure and method for making the same is disclosed. In an aspect, a FET structure comprises a gate structure, disposed between a first vertical source/drain (S/D) structure and a second vertical S/D structure, the gate structure comprising a channel structure comprising a plurality of vertically-stacked, horizontal channels connecting the first vertical S/D structure to the second vertical S/D structure horizontally through a vertical metal gate structure that at least partially surrounds the plurality of horizontal channels. The FET also comprises a backside inter-layer dielectric (ILD) layer disposed below the vertical metal gate structure, wherein a first thickness of the vertical metal gate structure below a bottom channel of the plurality of horizontal channels is larger than a second thickness of the vertical metal gate structure between adjacent channels of the plurality of horizontal channels.

公开(公告)号：US20250098302A1

公开(公告)日：2025-03-20

申请号：US18469505

申请日：2023-09-18

Applicant: QUALCOMM Incorporated

Inventor： Shreesh NARASIMHA ,  Yan SUN ,  Deepak SHARMA

IPC: H01L27/12

Abstract: Compact logic cells using full backside connectivity are disclosed. In an aspect, a semiconductor device comprises a plurality of integrated circuit cells comprising: gates separated by source/drain (S/D) structures and comprising at least one channel extending through a metal structure and connecting adjacent S/D structures to each other, at least one gate forming a gate-all-around field effect transistor; an FS contact electrically connecting to an S/D structure; an FS contact electrically connecting to a gate; a frontside (FS) inter-layer dielectric (ILD) on the gates and S/D structures; FS metal zero interconnects disposed on the FS-ILD, one being electrically connected to an FS contact; a BS contact electrically connecting to an S/D structure; a BS contact electrically connecting to a gate; a backside (BS) ILD disposed on the gates and S/D structures; and BS metal zero interconnects disposed on the BS-ILD, one being electrically connected to a BS contact.