公开(公告)号：US20190027554A1

公开(公告)日：2019-01-24

申请号：US15816295

申请日：2017-11-17

Applicant: QUALCOMM Incorporated

Inventor： Ye LU ,  Yun YUE ,  Phanikumar KONKAPAKA ,  Bin YANG ,  Chuan-Hsing CHEN

IPC: H01L29/06 ,  H01L23/522

Abstract: A metal-oxide-semiconductor (MOS) device for radio frequency (RF) applications may include a guard ring. The guard ring may surround the MOS device and at least one other MOS device. The MOS device may further include a level zero contact layer coupled to a first interconnect layer through level zero interconnects and vias. The first interconnect layer may be for routing to the MOS device.

公开(公告)号：US20180331198A1

公开(公告)日：2018-11-15

申请号：US15709332

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Phanikumar KONKAPAKA

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  G06F17/50

CPC classification number: H01L29/4966 ,  G06F17/5045 ,  G06F17/5081 ,  H01L21/823431 ,  H01L21/823493 ,  H01L27/0886

Abstract: A method of manufacturing a thin gate oxide N-type metal-oxide-semiconductor (NMOS) zero threshold voltage (ZVT) field effect transistor (FET) and an NMOS medium gate oxide native FET with a semiconductor manufacturing process eliminates the addition of halo masks. In one instance, the method includes selecting a gate stack to create the thin gate oxide NMOS ZVT FET or the NMOS medium gate oxide native FET when combined with blocking a P-type well implant and/or blocking a threshold voltage implant. The method also includes fabricating, on a semiconductor substrate, the selected gate stack. The method further includes blocking the P-type well implant and/or blocking the threshold voltage implant to obtain the thin gate oxide NMOS ZVT FET or the NMOS medium gate oxide native FET.

公开(公告)号：US20180323316A1

公开(公告)日：2018-11-08

申请号：US15709362

申请日：2017-09-19

Applicant: QUALCOMM Incorporated

Inventor： Phanikumar KONKAPAKA

IPC: H01L29/93 ,  H03B5/12 ,  H01L29/49

CPC classification number: H01L29/93 ,  H01L29/4966 ,  H03B5/1228 ,  H03B2200/004 ,  H03B2200/009 ,  H04B1/40

Abstract: An integrated circuit formed with a process that enables multiple types of gate stacks improves a quality factor of metal oxide semiconductor (MOS) varactors at the device level. In one instance, the integrated circuit includes multiple first type transistors having a first gate stack with a first resistance and multiple second type transistors having a second gate stack with a second resistance that is higher than the first resistance. The integrated circuit also includes a metal oxide semiconductor varactor having the first gate stack with the first resistance.