公开(公告)号：US09520988B1

公开(公告)日：2016-12-13

申请号：US14817934

申请日：2015-08-04

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Ohjoon Kwon

IPC: H04L7/00 ,  H04L27/20 ,  H04L27/227 ,  H04B1/40

CPC classification number: H04L7/0087 ,  H04B1/40 ,  H04L7/0083 ,  H04L25/14 ,  H04L25/4923 ,  H04L27/0002 ,  H04L27/20 ,  H04L27/227

Abstract: Systems, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Two Integrated Circuit (IC) devices may be collocated in an electronic apparatus and communicatively coupled through a 3-wire, 3-phase interface. A data transfer method operational on a first of the two or more devices includes determining presence of a misalignment of the 3-wire communication link involving two or more wires, and inverting a first bit of a 3-bit symbol encoded in a transition of signaling state of the 3-wire communication link when the misalignment of the 3-wire communication link is determined to affect phase relationships between two or more signals carried on the three wires, such that inverting the first bit corrects the phase relationships between the two or more signals. A version of the 3-phase signal may be communicated in a different phase state through each of three wires.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 两个集成电路（IC）器件可以并置在电子设备中并且通过3线，3相接口通信耦合。 在两个或更多个设备中的第一个上可操作的数据传输方法包括确定存在涉及两条或更多条导线的3线通信链路的未对准，并且反转信令转换中编码的3位符号的第一位 当确定3线通信链路的未对准被确定为影响在三条线路上承载的两个或更多个信号之间的相位关系时，3线通信链路的状态，使得反转第一比特校正两个或更多个之间的相位关系 信号。 三相信号的版本可以通过三条线中的每一条在不同的相位状态下传送。

公开(公告)号：US20170041130A1

公开(公告)日：2017-02-09

申请号：US15270853

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Ohjoon Kwon

IPC: H04L7/00 ,  H04L27/227 ,  H04L27/00 ,  H04L27/20

CPC classification number: H04L7/0087 ,  H04B1/40 ,  H04L7/0083 ,  H04L25/14 ,  H04L25/4923 ,  H04L27/0002 ,  H04L27/20 ,  H04L27/227

Abstract: Systems, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Two Integrated Circuit (IC) devices may be collocated in an electronic apparatus and communicatively coupled through a 3-wire, 3-phase interface. A data transfer method operational on a first of the two or more devices includes determining presence of a misalignment of the 3-wire communication link involving two or more wires, and inverting a first bit of a 3-bit symbol encoded in a transition of signaling state of the 3-wire communication link when the misalignment of the 3-wire communication link is determined to affect phase relationships between two or more signals carried on the three wires, such that inverting the first bit corrects the phase relationships between the two or more signals. A version of the 3-phase signal may be communicated in a different phase state through each of three wires.

Abstract translation: 描述了促进数据传输的系统，方法和装置，特别是在电子设备内的两个设备之间。 两个集成电路（IC）器件可以并置在电子设备中并且通过3线，3相接口通信耦合。 在两个或更多个设备中的第一个上可操作的数据传输方法包括确定存在涉及两条或更多条导线的3线通信链路的未对准，并且反转信令转换中编码的3位符号的第一位 当确定3线通信链路的未对准被确定为影响在三条线路上承载的两个或更多个信号之间的相位关系时，3线通信链路的状态，使得反转第一比特校正两个或更多个之间的相位关系 信号。 三相信号的版本可以通过三条线中的每一条在不同的相位状态下传送。

公开(公告)号：US10049067B2

公开(公告)日：2018-08-14

申请号：US15367071

申请日：2016-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xiaohua Kong ,  Deqiang Song ,  Zhi Zhu ,  Ohjoon Kwon

IPC: G06F13/38 ,  G06F13/42 ,  G06F3/14

Abstract: An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface. A second controller for the dual-protocol physical layer interface is located closer on a semiconductor die to the dual-protocol physical layer interface than the first controller.

公开(公告)号：US20180157609A1

公开(公告)日：2018-06-07

申请号：US15367071

申请日：2016-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xiaohua Kong ,  Deqiang Song ,  Zhi Zhu ,  Ohjoon Kwon

IPC: G06F13/38 ,  G06F13/42

CPC classification number: G06F13/385 ,  G06F3/14 ,  G06F13/4282

Abstract: An on-chip passive transmission channel is provided for the propagation of serialized data from a first controller to a dual-protocol physical layer interface. A second controller for the dual-protocol physical layer interface is located closer on a semiconductor die to the dual-protocol physical layer interface than the first controller.

公开(公告)号：US09621333B2

公开(公告)日：2017-04-11

申请号：US15270853

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： George Alan Wiley ,  Ohjoon Kwon

IPC: H04L7/00 ,  H04L27/20 ,  H04L27/227 ,  H04L27/00 ,  H04B1/40

CPC classification number: H04L7/0087 ,  H04B1/40 ,  H04L7/0083 ,  H04L25/14 ,  H04L25/4923 ,  H04L27/0002 ,  H04L27/20 ,  H04L27/227

Abstract: Systems, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Two Integrated Circuit (IC) devices may be collocated in an electronic apparatus and communicatively coupled through a 3-wire, 3-phase interface. A data transfer method operational on a first of the two or more devices includes determining presence of a misalignment of the 3-wire communication link involving two or more wires, and inverting a first bit of a 3-bit symbol encoded in a transition of signaling state of the 3-wire communication link when the misalignment of the 3-wire communication link is determined to affect phase relationships between two or more signals carried on the three wires, such that inverting the first bit corrects the phase relationships between the two or more signals. A version of the 3-phase signal may be communicated in a different phase state through each of three wires.

公开(公告)号：US20170039163A1

公开(公告)日：2017-02-09

申请号：US15332756

申请日：2016-10-24

Applicant: QUALCOMM Incorporated

Inventor： Dhaval Sejpal ,  Shih-Wei Chou ,  Chulkyu Lee ,  Ohjoon Kwon ,  George Alan Wiley

IPC: G06F13/42

CPC classification number: G06F13/4291 ,  G06F13/4278 ,  H04L25/4917

Abstract: Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. One method includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.

Abstract translation: 公开了用于在多线接口上的传输中的错误检测的装置，系统和方法。 一种方法包括提供多个发射时钟信号，包括具有不同相移的发射时钟信号，确定将在两条连续发射的符号之间的边界处在3线接口的每条线路上发生的信令状态的转换类型， 以及选择所述多个发射时钟信号之一以启动所述三相接口的每条线路上的信令状态的转换。 选择多个发射时钟信号中的一个可以包括当信令状态的转换在未驱动状态下终止时选择第一发射时钟信号，以及当信令状态的转变在未驱动状态开始时选择第二发射时钟信号。 第一个启动时钟信号中的边沿可能发生在第二个启动时钟信号的相应边沿之前。

公开(公告)号：US10289600B2

公开(公告)日：2019-05-14

申请号：US15332756

申请日：2016-10-24

Applicant: QUALCOMM Incorporated

Inventor： Dhaval Sejpal ,  Shih-Wei Chou ,  Chulkyu Lee ,  Ohjoon Kwon ,  George Alan Wiley

IPC: G06F13/20 ,  G06F13/42 ,  H04L25/49 ,  H04L7/00

Abstract: A method for error detection in transmissions on a multi-wire interface includes providing a plurality of launch clock signals, including launch clock signals having a different phase shifts, determining a type of transition in signaling state that will occur on each wire of the 3-wire interface at a boundary between two consecutively transmitted symbols, and selecting one of the plurality of launch clock signals to initiate the transition of signaling state on each wire of the 3-phase interface. Selecting one of the plurality of launch clock signals may include selecting a first launch clock signal when the transition in signaling state terminates at an undriven state, and selecting a second launch clock signal when the transition in signaling state begins at an undriven state. An edge in the first launch clock signal may occur before a corresponding edge in the second launch clock signal.

公开(公告)号：US09496879B1

公开(公告)日：2016-11-15

申请号：US14842644

申请日：2015-09-01

Applicant: QUALCOMM Incorporated

Inventor： Ying Duan ,  Chulkyu Lee ,  Shih-Wei Chou ,  Harry Dang ,  Ohjoon Kwon

IPC: H03D3/24 ,  H03L7/08 ,  H03L7/081 ,  H04L7/00 ,  H04L7/033

CPC classification number: H03L7/0807 ,  H03L7/0812 ,  H04L7/0037 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/04 ,  H04L25/4917

Abstract: Methods, apparatus, and systems for data communication over a multi-wire, multi-phase interface are disclosed. A method of data communication includes configuring a clock recovery circuit to provide a first clock signal that includes a pulse for each symbol transmitted on the interface, where symbols are transmitted on the interface at a first frequency, adjusting a loop delay of the clock recovery circuit to modify the first clock to have a second frequency that is no more than half the first frequency, where the clock recovery circuit generates a pulse in the first clock signal for a first of an integer number of symbols and suppresses pulse generation for other symbols in the integer number of symbols, configuring a clock generation circuit to provide a second clock signal, and capturing symbols from the interface using the first clock signal and the second clock signal.

Abstract translation: 公开了通过多线，多相接口进行数据通信的方法，装置和系统。 一种数据通信方法包括配置时钟恢复电路以提供第一时钟信号，该第一时钟信号包括在接口上发送的每个符号的脉冲，其中符号以第一频率在接口上发送，调整时钟恢复电路的环路延迟 修改第一时钟以具有不超过第一频率的一半的第二频率，其中时钟恢复电路在第一时钟信号中产生用于整数符号中的第一个的脉冲，并且抑制其他符号的脉冲产生 整数个符号，配置时钟发生电路以提供第二时钟信号，以及使用第一时钟信号和第二时钟信号从接口捕获符号。

公开(公告)号：US09485080B1

公开(公告)日：2016-11-01

申请号：US14842610

申请日：2015-09-01

Applicant: QUALCOMM Incorporated

Inventor： Ying Duan ,  Chulkyu Lee ,  Harry Dang ,  Ohjoon Kwon

IPC: H04L7/00 ,  H04L5/00 ,  H04L7/08

CPC classification number: H04L7/0008 ,  H03K5/135 ,  H04L5/0048 ,  H04L7/033 ,  H04L7/04 ,  H04L7/08 ,  H04L25/0272 ,  H04L25/4923

Abstract: Methods, apparatus, and systems for clock calibration are disclosed. A method for clock data recovery circuit calibration includes configuring a first clock recovery circuit to provide a clock signal that has a first frequency and that includes a single pulse for each symbol transmitted on a 3-wire, 3-phase interface, and calibrating the first clock recovery circuit by incrementally increasing a delay period provided by a delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that is less than the first frequency and, when the first clock recovery circuit has a frequency that is less than the first frequency, incrementally decreasing the delay period provided by the delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that matches the first frequency.

Abstract translation: 公开了用于时钟校准的方法，装置和系统。 一种用于时钟数据恢复电路校准的方法包括配置第一时钟恢复电路以提供具有第一频率的时钟信号，并且对于在3线3相接口上传输的每个符号包括单个脉冲，并且校准第一频率 时钟恢复电路，通过逐渐增加由第一时钟恢复电路的延迟元件提供的延迟时间，直到由第一时钟恢复电路提供的时钟信号具有小于第一频率的频率，并且当第一时钟恢复电路具有 小于第一频率的频率，逐渐减小由第一时钟恢复电路的延迟元件提供的延迟周期，直到由第一时钟恢复电路提供的时钟信号具有与第一频率匹配的频率。