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公开(公告)号：US10749481B2
公开(公告)日：2020-08-18
申请号：US15956026
申请日：2018-04-18
Applicant: QUALCOMM Incorporated
Inventor： Bo Sun , Yi Tang , Daniel Butterfield
Abstract: Aspects generally relate to reducing delay, or phase jitter, in high speed signals transmission. Variations in power supply to ground potential changes the amount of delay introduced by transmit circuitry into the signal being transmitted, resulting in jitter, or phase noise, in the transmitted signal. To reduce phase jitter, or phase noise, aspects disclosed include a variable impedance circuit coupled to the signal distribution network, the impedance level of the variable impedance circuit is adjusted in response to variation in the supply to ground potential, such that the delay introduced by the impedance compensates for changes in the delay due to variations in supply to ground potential, resulting in substantially constant delay.
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Patent Agency Ranking
公开(公告)号：US20140253206A1
公开(公告)日：2014-09-11
申请号：US13794066
申请日：2013-03-11
Applicant: QUALCOMM INCORPORATED
IPC: H03H11/04
CPC classification number: H03H11/04 , H03H11/245
Abstract: A low-pass filter circuit is described. The low-pass filter circuit includes a pseudo-resistor. The pseudo-resistor includes at least one metal-oxide-semiconductor field-effect transistor. The at least one metal-oxide-semiconductor field-effect transistor receives a digital power supply domain signal. The low-pass filter circuit also includes a capacitor. The capacitor is coupled to the pseudo-resistor. The capacitor provides a filtered signal. The low-pass filter circuit may pass digital signal transitions and provide low-pass filtering when there is no signal transition.
Abstract translation: 描述低通滤波器电路。 低通滤波电路包括伪电阻。 该伪电阻器包括至少一个金属氧化物半导体场效应晶体管。 所述至少一个金属氧化物半导体场效应晶体管接收数字电源域信号。 低通滤波器电路还包括电容器。 电容器耦合到伪电阻。 电容器提供滤波信号。 低通滤波器电路可以通过数字信号转换，并且当没有信号转换时提供低通滤波。
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3.发明授权公开(公告)号：US09100026B2
公开(公告)日：2015-08-04
申请号：US13938727
申请日：2013-07-10
Applicant: QUALCOMM Incorporated
Inventor： Gary John Ballantyne , Bo Sun , Yi Tang , Zixiang Yang , Masoud Ensafdaran
CPC classification number: H03L7/0991 , H03B5/1265 , H03B2200/0088 , H03B2201/025 , H03B2202/017 , H03J5/24 , H03J2200/10 , H03J2200/36 , H03L7/099 , H03L2207/50
Abstract: One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.
Abstract translation: 一个特征涉及包含可变电容器和降噪电路的数字控制振荡器（DCO）。 可变电容器具有控制DCO的输出频率的可变电容值。 可变电容值基于由第一电容器组提供的第一组电容值，由第二电容器组提供的第二组电容值和由辅助电容器组提供的辅助组电容值。 噪声降低电路适于通过调整辅助电容电容值来调节可变电容值，同时保持第一组电容值和/或第二组电容值中的至少一个基本上不变。 在调整可变电容值之前，噪声降低电路可以确定接收的输入DCO控制字在电容器组敏感边界之间转变。
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公开(公告)号：US08957712B2
公开(公告)日：2015-02-17
申请号：US13842481
申请日：2013-03-15
Applicant: QUALCOMM Incorporated
CPC classification number: H03M1/50 , G04F10/005 , H03L7/08 , H03L7/0991 , H03L2207/50
Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.
Abstract translation: 时间 - 数字转换器将参考时钟信号和振荡信号的转换时间之间的差异转换成数值信号，其数值信号与转换时序差成比例。 该时间 - 数字转换器包括边缘检测器，时间 - 电压转换器和模 - 数转换器。 边缘检测器适于在参考时钟信号的每个周期期间检测最靠近参考时钟信号的边缘的振荡信号的边沿（跃迁）。 时间 - 电压转换器适于产生与所检测的振荡信号的边沿与基准时钟信号的边沿之间的时间差成比例的模拟信号。 模拟 - 数字转换器适于将模拟信号转换成数字信号，该数字信号的值与振荡信号的检测到的边沿的出现与参考时钟信号的边沿之间的差成比例。
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公开(公告)号：US20140266353A1
公开(公告)日：2014-09-18
申请号：US13842481
申请日：2013-03-15
Applicant: QUALCOMM INCORPORATED
CPC classification number: H03M1/50 , G04F10/005 , H03L7/08 , H03L7/0991 , H03L2207/50
Abstract: A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal.
Abstract translation: 时间 - 数字转换器将参考时钟信号和振荡信号的转换时间之间的差异转换成数值信号，其数值信号与转换时序差成比例。 该时间 - 数字转换器包括边缘检测器，时间 - 电压转换器和模 - 数转换器。 边缘检测器适于在参考时钟信号的每个周期期间检测最靠近参考时钟信号的边缘的振荡信号的边沿（跃迁）。 时间 - 电压转换器适于产生与所检测的振荡信号的边沿与基准时钟信号的边沿之间的时间差成比例的模拟信号。 模拟 - 数字转换器适于将模拟信号转换成数字信号，该数字信号的值与振荡信号的检测到的边沿的出现与参考时钟信号的边沿之间的差成比例。
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6.发明申请公开(公告)号：US20150015343A1
公开(公告)日：2015-01-15
申请号：US13938727
申请日：2013-07-10
Applicant: QUALCOMM Incorporated
Inventor： Gary John Ballantyne , Bo Sun , Yi Tang , Zixiang Yang , Masoud Ensafdaran
IPC: H03L7/099
CPC classification number: H03L7/0991 , H03B5/1265 , H03B2200/0088 , H03B2201/025 , H03B2202/017 , H03J5/24 , H03J2200/10 , H03J2200/36 , H03L7/099 , H03L2207/50
Abstract: One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary.
Abstract translation: 一个特征涉及包含可变电容器和降噪电路的数字控制振荡器（DCO）。 可变电容器具有控制DCO的输出频率的可变电容值。 可变电容值基于由第一电容器组提供的第一组电容值，由第二电容器组提供的第二组电容值和由辅助电容器组提供的辅助组电容值。 噪声降低电路适于通过调整辅助电容电容值来调节可变电容值，同时保持第一组电容值和/或第二组电容值中的至少一个基本上不变。 在调整可变电容值之前，噪声降低电路可以确定接收的输入DCO控制字在电容器组敏感边界之间转变。
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