公开(公告)号：US09734890B1

公开(公告)日：2017-08-15

申请号：US15142306

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Michael Drop ,  Vaishnav Srinivas ,  Philip Clovis

IPC: G11C11/409 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/1678 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

公开(公告)号：US09734878B1

公开(公告)日：2017-08-15

申请号：US15142316

申请日：2016-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Farrukh Aquil ,  Michael Drop ,  Vaishnav Srinivas ,  Philip Clovis

IPC: G11C7/10 ,  G11C11/408 ,  G11C11/407 ,  G11C11/4076 ,  G06F13/42 ,  G06F13/16

CPC classification number: G11C11/4093 ,  G06F13/1678 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.