公开(公告)号：US09270287B2

公开(公告)日：2016-02-23

申请号：US14490952

申请日：2014-09-19

Applicant: QUALCOMM Incorporated

Inventor： Zhi Zhu ,  Xiaohua Kong ,  Nam Van Dang

IPC: H03L7/08 ,  H03L7/099 ,  H04L7/027 ,  H04L7/033

CPC classification number: H03L7/0802 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/0995 ,  H04L7/0276 ,  H04L7/0338

Abstract: A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.

Abstract translation: 门控压控振荡器具有四个相同结构的延迟单元，每个延迟单元通过连接到其他延迟单元的相同数量的输入端而具有相同的输出负载。 可选地，四相采样时钟从延迟单元输出中选择并在四相采样器处采样输入信号。 可选地，边沿检测器将门控压控振荡器的相位同步到NRZ位。 可选地，可变采样率选择来自延迟单元的不同相位以选择以较低速率对NRZ位进行采样。 可选地，脉冲宽度调制（PWM）模式将采样时钟的相位同步到采样PWM符号并恢复编码比特。

公开(公告)号：US20160378166A1

公开(公告)日：2016-12-29

申请号：US15260355

申请日：2016-09-09

Applicant: QUALCOMM Incorporated

Inventor： Cheng Zhong ,  Nam Van Dang ,  Hung Quoc Vuong ,  Xiaohua Kong

IPC: G06F1/32 ,  G06F11/30 ,  G06F11/22 ,  G06F13/40

Abstract: An electronic device includes a receiver sense circuit configured to generate a detection signal responsive to detecting a connection to a sink device via a connector. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to enable a direct current (DC) voltage source based on the detection signal received from the receiver sense circuit.

Abstract translation: 电子设备包括接收机感测电路，其被配置为响应于经由连接器检测到与设备的连接而产生检测信号。 电子设备还包括耦合到热插拔检测（HPD）接口的控制器。 控制器被配置为基于从接收机感测电路接收的检测信号来启用直流（DC）电压源。

公开(公告)号：US20150301539A1

公开(公告)日：2015-10-22

申请号：US14254279

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Nam Van Dang ,  Rajeev Jain ,  Terrence Brian Remple ,  Jingcheng Zhuang ,  Mong Chit Wong

IPC: G05F1/46

CPC classification number: G05F1/468 ,  G05F3/30

Abstract: A series of current repeaters with localized feedback is provided. Each current that precedes a subsequent current repeater in the series is configured to receive a feedback current from the subsequent current repeater and generate an error signal accordingly with a differential amplifier so as to reduce current repetition errors that would otherwise result from an offset voltage in the differential amplifier.

Abstract translation: 提供了一系列具有局部反馈的电流中继器。 在串联中的随后的当前中继器之前的每个电流被配置为从随后的当前中继器接收反馈电流，并且相应地使用差分放大器产生误差信号，以便减少否则由于偏置电压而产生的电流重复误差 差分放大器。

公开(公告)号：US20150008967A1

公开(公告)日：2015-01-08

申请号：US14490952

申请日：2014-09-19

Applicant: QUALCOMM Incorporated

Inventor： Zhi Zhu ,  Xiaohua Kong ,  Nam Van Dang

IPC: H03L7/08

CPC classification number: H03L7/0802 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/0995 ,  H04L7/0276 ,  H04L7/0338

Abstract: A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.

Abstract translation: 门控压控振荡器具有四个相同结构的延迟单元，每个延迟单元通过连接到其他延迟单元的相同数量的输入端而具有相同的输出负载。 可选地，四相采样时钟从延迟单元输出中选择并在四相采样器处采样输入信号。 可选地，边沿检测器将门控压控振荡器的相位同步到NRZ位。 可选地，可变采样率选择来自延迟单元的不同相位以选择以较低速率对NRZ位进行采样。 可选地，脉冲宽度调制（PWM）模式将采样时钟的相位同步到采样PWM符号并恢复编码比特。

公开(公告)号：US09465424B2

公开(公告)日：2016-10-11

申请号：US14167000

申请日：2014-01-29

Applicant: QUALCOMM Incorporated

Inventor： Cheng Zhong ,  Nam Van Dang ,  Hung Q. Vuong ,  Xiaohua Kong

IPC: G06F1/26 ,  G06F1/16 ,  G06F1/32

CPC classification number: G06F1/3278 ,  G06F1/1632 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3281 ,  G06F11/2289 ,  G06F11/3041 ,  G06F11/3048 ,  G06F11/3051 ,  G06F11/3089 ,  G06F13/4022 ,  G06F13/4081 ,  Y02D10/151 ,  Y10T307/76

Abstract: In a particular embodiment, an electronic device includes a direct current (DC) voltage source coupled to a DC interface. The electronic device includes a receiver sense circuit configured to detect a connection of the electronic device to a sink device via a connector without consuming power from the DC voltage source. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to receive a detection signal from the receiver sense circuit, selectively control a switch to enable and disable the DC voltage source based on the detection signal, detect an HPD signal at the HPD interface after enabling the DC voltage source, and disable the receiver sense circuit in response to detecting the HPD signal.

Abstract translation: 在特定实施例中，电子设备包括耦合到DC接口的直流（DC）电压源。 电子设备包括接收器感测电路，其被配置为经由连接器检测电子设备到宿设备的连接，而不消耗来自DC电压源的电力。 电子设备还包括耦合到热插拔检测（HPD）接口的控制器。 控制器被配置为从接收器感测电路接收检测信号，选择性地控制开关以基于检测信号启用和禁用DC电压源，在启用直流电压源之后检测HPD接口处的HPD信号，并禁用 接收机感测电路响应于检测到HPD信号。

公开(公告)号：US09037437B2

公开(公告)日：2015-05-19

申请号：US14105213

申请日：2013-12-13

Applicant: QUALCOMM Incorporated

Inventor： Miao Li ,  Xiaohua Kong ,  Nam Van Dang ,  Cheng Zhong

IPC: G06F11/30 ,  G01R31/3177 ,  G09G5/00 ,  G06F1/04

CPC classification number: G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract translation: 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径中的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

公开(公告)号：US20140101507A1

公开(公告)日：2014-04-10

申请号：US14105213

申请日：2013-12-13

Applicant: QUALCOMM INCORPORATED

Inventor： Miao Li ,  Xiaohua Kong ,  Nam Van Dang ,  Cheng Zhong

IPC: G01R31/3177 ,  G06F1/04

CPC classification number: G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract translation: 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径中的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

公开(公告)号：US10459512B2

公开(公告)日：2019-10-29

申请号：US15260355

申请日：2016-09-09

Applicant: QUALCOMM Incorporated

Inventor： Cheng Zhong ,  Nam Van Dang ,  Hung Quoc Vuong ,  Xiaohua Kong

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/16 ,  G06F1/26 ,  G06F1/3206 ,  G06F11/22 ,  G06F11/30 ,  G06F13/40

Abstract: An electronic device includes a receiver sense circuit configured to generate a detection signal responsive to detecting a connection to a sink device via a connector. The electronic device further includes a controller coupled to a hot plug detect (HPD) interface. The controller is configured to enable a direct current (DC) voltage source based on the detection signal received from the receiver sense circuit.

公开(公告)号：US09971730B2

公开(公告)日：2018-05-15

申请号：US14739439

申请日：2015-06-15

Applicant: QUALCOMM Incorporated

Inventor： Terrence Brian Remple ,  Nam Van Dang ,  Sassan Shahrokhinia

IPC: G06F13/14 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F13/426 ,  G06F13/382 ,  G06F13/385 ,  G06F13/4221 ,  G06F13/4282 ,  G06F2213/0038 ,  G06F2213/3812

Abstract: A link layer to physical layer (PHY) serial interface is disclosed. In one aspect, a system on a chip (SoC) integrated circuit (IC) includes a link layer circuit, and a remote IC includes a Universal Serial Bus (USB) PHY circuit. A bus having four or fewer wires connects the two ICs. A link bridge communicates with the link layer circuit and serializes USB Transceiver Macrocell Interface (UTMI) signaling received from the link layer circuit as high speed (HS) USB messages for transmission to the remote IC. The link bridge also receives HS messages from the USB PHY circuit on the remote IC. The link bridge deserializes the HS messages to extract UTMI signaling and passes the extracted UTMI signaling to the link layer circuit.

公开(公告)号：US20160266598A1

公开(公告)日：2016-09-15

申请号：US14643981

申请日：2015-03-10

Applicant: QUALCOMM Incorporated

Inventor： Mong Chit Wong ,  Nam Van Dang ,  Rajeev Jain ,  Bo-Ren Wang ,  Sassan Shahrokhinia

IPC: G05F3/26

CPC classification number: G05F3/267 ,  G05F3/30

Abstract: Systems and methods for producing reference voltages are disclosed. An example bandgap reference circuit includes a core bandgap module that produces a bias control for biasing the gate of a transistor to produce a proportional to absolute temperature current. The core bandgap module may use an operational amplifier that uses auto-calibration to reduce its input offset voltage. A trimming module uses the bias control to produce a proportional to absolute temperature current that is combined with a trim current and supplied to a resistor and diode to produce a trimmed bandgap voltage. The trimmed bandgap voltage is buffered to produce a reference voltage output. The trim current may be set based on a room temperature measurement of the reference voltage output.

Abstract translation: 公开了用于产生参考电压的系统和方法。 一个示例性带隙基准电路包括一个核心带隙模块，其产生用于偏置晶体管栅极以产生与绝对温度电流成比例的偏置控制。 核心带隙模块可以使用使用自动校准的运算放大器来减少其输入失调电压。 修整模块使用偏置控制来产生与绝缘温度电流成比例的结合微调电流并提供给电阻和二极管以产生修整的带隙电压。 修整的带隙电压被缓冲以产生参考电压输出。 可以基于参考电压输出的室温测量来设置微调电流。