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公开(公告)号：US10114443B2
公开(公告)日：2018-10-30
申请号：US15441124
申请日：2017-02-23
Applicant: QUALCOMM Incorporated
Inventor： Rajat Mittal , Madan Krishnappa , Rajit Chandra , Mohammad Tamjidi
Abstract: A thermal controller for managing thermal energy of a multi-core processor is provided. The cores include a first core processing a load and remaining cores. The thermal controller is configured to determine that a temperature of the first core is greater than a first threshold, determine a temperature of a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold, and determine whether the temperature of the second core is greater than or less than a second threshold. The thermal controller is configured to transfer at least a portion of the load of the first core to the second core in response to determining that the temperature of the first core is greater than the first threshold and based on whether the temperature of the second core is greater than or less than the second threshold.
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公开(公告)号：US10401941B2
公开(公告)日：2019-09-03
申请号：US15425980
申请日：2017-02-06
Applicant: QUALCOMM Incorporated
Inventor： Harshat Pant , Ramprasath Vilangudipitchai , Srijith Nair , Mohammad Tamjidi
IPC: G06F1/32 , G06F1/3287 , G06F1/3296 , G06F1/10 , H03K5/13
Abstract: An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.
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公开(公告)号：US20180224921A1
公开(公告)日：2018-08-09
申请号：US15425980
申请日：2017-02-06
Applicant: QUALCOMM Incorporated
Inventor： Harshat Pant , Ramaprasath Vilangudipitchai , Srijith Nair , Mohammad Tamjidi
IPC: G06F1/32
CPC classification number: G06F1/3287 , G06F1/10 , G06F1/3296 , H03K5/13 , Y02D10/171
Abstract: An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.
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Patent Agency Ranking
公开(公告)号：US20240370369A1
公开(公告)日：2024-11-07
申请号：US18484950
申请日：2023-10-11
Applicant: QUALCOMM Incorporated
Inventor： George Patsilaras , Sparsh Singhai , Subbarao Palacharla , Simon Peter William Booth , Girish Bhat , Ling Feng Huang , Scott Cheng , Yen-Kuan Wu , Mohammad Tamjidi
IPC: G06F12/06 , G06F12/0873
Abstract: Reconfigurable shared memory systems, and related processor-based systems and methods are disclosed. The reconfigurable shared memory system can be included in a processor-based system to provide memory for data storage. In exemplary aspects, the reconfigurable shared memory system not only includes the dedicated memory and the general memory (e.g., system cache memory), but also includes a reconfigurable memory. The reconfigurable memory can be configured as either part of addressable memory space of the dedicated memory if an application requires such additional dedicated memory, and/or configured as part of the addressable memory space of the general memory to provide additional memory to other clients for increased processing performance if such reconfigurable memory is not needed as part of the dedicated memory. The dedicated memory does not have to be sized to the worst-case size requirements of a given application.
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公开(公告)号：US09612636B2
公开(公告)日：2017-04-04
申请号：US14497258
申请日：2014-09-25
Applicant: QUALCOMM Incorporated
Inventor： Matthew Levi Severson , Shih-Hsin Jason Hu , Dipti Ranjan Pal , Madan Krishnappa , Jeffrey Gemar , Noman Ahmed , Mohammad Tamjidi , Mark Kempfert
CPC classification number: G06F1/26 , G06F1/32 , G06F1/3287 , G06F9/4405 , Y02D10/171
Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.
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公开(公告)号：US09817470B2
公开(公告)日：2017-11-14
申请号：US15052786
申请日：2016-02-24
Applicant: QUALCOMM Incorporated
Inventor： Suresh Sugumar , Jeffrey Gemar , Ali Taha , Amy Derbyshire , Tao Xue , Mohammad Tamjidi , Rajat Mittal
IPC: G06F1/32
CPC classification number: G06F1/3296 , G06F1/3206 , G06F1/3243 , G06F1/3287 , G06F9/30189 , G06F9/3836 , G06F9/3861 , G06F9/3885 , Y02D10/152
Abstract: An apparatus includes a first circuit and a second circuit sharing an instruction stream. A voltage controller circuit is configured to provide an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream. In another aspect, a method of operating a power management function is presented. The method includes providing an instruction stream for a first circuit and a second circuit and providing selectively an operation voltage and at least one low-power voltage to the second circuit independent of a supply voltage of the first circuit in response to a sequence of the instruction stream.
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公开(公告)号：US09652026B2
公开(公告)日：2017-05-16
申请号：US14578437
申请日：2014-12-21
Applicant: QUALCOMM INCORPORATED
Inventor： Hee-Jun Park , Parag Arun Agashe , Mohammad Tamjidi
CPC classification number: G06F1/324 , G06F1/1613 , G06F1/3203 , G06F1/3206 , G06F1/3212 , G06F1/3234 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172 , Y02D10/174 , Y02D10/24
Abstract: Various embodiments of methods and systems for dynamically adjusting a peak dynamic power threshold are disclosed. Advantageously, embodiments of the solution for peak dynamic power management optimize a peak dynamic power threshold based on estimations of real-time leakage current levels and/or actual power supply levels to a power domain of a system on a chip (“SoC”). In this way, embodiments of the solution ensure that a maximum amount of available power supply is allocated to dynamic power consumption for processing workloads at an optimum performance or quality of service (“QoS”) level without risking that the total power consumption (leakage power consumption+dynamic power consumption) for the power domain exceeds the power supply capacity.
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公开(公告)号：US09582052B2
公开(公告)日：2017-02-28
申请号：US14675409
申请日：2015-03-31
Applicant: QUALCOMM Incorporated
Inventor： Rajat Mittal , Madan Krishnappa , Rajit Chandra , Mohammad Tamjidi
CPC classification number: G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F9/4856 , G06F9/5088 , G06F9/5094 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D10/172 , Y02D10/22 , Y02D10/24 , Y02D10/32
Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a UE. The UE has a processor including a plurality of cores. The plurality of cores includes a first core and remaining cores. The UE determines a temperature of the first core of the plurality of cores. The first core processes a load. The UE determines that the temperature of the first core is greater than a first threshold. The UE determines that the temperature of the first core is not greater than a second threshold. The second threshold is greater than the first threshold. The UE transfers at least a portion of the load of the first core to a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold.
Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置可以是UE。 UE具有包括多个核的处理器。 多个芯包括第一芯和剩余芯。 UE确定多个核心的第一核心的温度。 第一个核心处理一个负载。 UE确定第一核的温度大于第一阈值。 UE确定第一核心的温度不大于第二阈值。 第二阈值大于第一阈值。 响应于确定第一核心的温度大于第一阈值，UE将第一核心的至少一部分负载传送到剩余核心的第二核心。
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