公开(公告)号：US10192813B2

公开(公告)日：2019-01-29

申请号：US13753193

申请日：2013-01-29

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Yang Du ,  Robert P. Gilmore

IPC: G06F17/50 ,  H01L21/768 ,  H01L23/498

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

公开(公告)号：US09483598B2

公开(公告)日：2016-11-01

申请号：US14617896

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Kambiz Samadi ,  Yang Du

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0688

Abstract: An intellectual property (IP) block design methodology for three-dimensional (3D) integrated circuits may comprise folding at least one two-dimensional (2D) block that has one or more circuit components into a 3D block that has multiple tiers, wherein the one or more circuit components in the folded 2D block may be distributed among the multiple tiers in the 3D block. Furthermore, one or more pins may be duplicated across the multiple tiers in the 3D block and the one or more duplicated pins may be connected to one another using one or more intra-block through-silicon-vias (TSVs) placed inside the 3D block.

Abstract translation: 用于三维（3D）集成电路的知识产权（IP）块设计方法可以包括将具有一个或多个电路组件的至少一个二维（2D）块折叠到具有多个层的3D块中，其中， 折叠的2D块中的多个电路组件可以分布在3D块中的多个层中。 此外，一个或多个引脚可以跨越3D块中的多个层复制，并且一个或多个复制引脚可以使用放置在3D块内部的一个或多个块内穿通硅通孔（TSV）彼此连接 。

公开(公告)号：US20190027435A1

公开(公告)日：2019-01-24

申请号：US16144127

申请日：2018-09-27

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/528 ,  H01L25/00 ,  H01L23/522 ,  H01L27/06 ,  H01L23/48 ,  H01L25/065

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

公开(公告)号：US09569380B2

公开(公告)日：2017-02-14

申请号：US14602505

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Karamvir Singh Chatha ,  Yang Du ,  Kambiz Samadi

IPC: G06F13/16 ,  H01L25/065 ,  G06F13/42 ,  H01L23/48 ,  H01L23/50 ,  H01L25/18 ,  H01L25/00 ,  H01L27/06

Abstract: Aspects disclosed in the detailed description include memory controller placement in a three-dimensional (3D) integrated circuit (IC) (3DIC) employing distributed through-silicon-via (TSV) farms. In this regard, in one aspect, a memory controller is disposed in a 3DIC based on a centralized memory controller placement scheme within the distributed TSV farm. The memory controller can be placed at a geometric center within multiple TSV farms to provide an approximately equal wire-length between the memory controller and each of the multiple TSV farms. In another aspect, multiple memory controllers are provided in a 3DIC based on a distributed memory controller placement scheme, in which each of the multiple memory controllers is placed adjacent to a respective TSV farm among the multiple TSV farms. By disposing the memory controller(s) based on the centralized memory controller placement scheme and/or the distributed memory controller placement scheme in the 3DIC, latency of memory access requests is minimized.

公开(公告)号：US09508615B2

公开(公告)日：2016-11-29

申请号：US14617901

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Kambiz Samadi ,  Pratyush Kamal ,  Yang Du

IPC: H01L23/58 ,  H01L21/66 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L22/20 ,  H01L22/32 ,  H01L23/5256 ,  H01L23/5382 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06596

Abstract: To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.

Abstract translation: 为了实现三维（3D）集成电路的低成本预键测试，主干管芯可以具有完全连接的二维（2D）时钟树，并且一个或多个非主干管芯可以具有多个隔离的2D时钟树 。 在各种实施例中，可以使用多个通硅通孔来连接骨干管芯和非骨干管芯上的时钟汇聚点，并且非骨干管芯中的隔离的2D时钟树可以通过可分离树（D-tree）进一步连接 ），其可以包括表示与非主干管芯中的2D时钟树相关联的汇之间的最短互连的直线最小生成树。 因此，在使用一个时钟探针焊盘进行粘合之前，主骨架和非主干裸片可以被分离和单独测试，并且在通过燃烧进行预键合测试之前，D树可以容易地从非主干模具移除 在与2D时钟树相关联的接收器处保险丝。

公开(公告)号：US09041448B2

公开(公告)日：2015-05-26

申请号：US13784915

申请日：2013-03-05

Applicant: QUALCOMM Incorporated

Inventor： Yang Du ,  Jing Xie ,  Kambiz Samadi

IPC: H03K3/289 ,  H01L25/065 ,  H01L25/00 ,  H01L27/06 ,  H03K3/037

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2924/0002 ,  H03K3/0372 ,  H01L2924/00

Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

Abstract translation: 公开了一种单片三维（3D）集成电路（IC）（3DIC）和相关方法中的触发器。 在一个实施例中，为3DIC提供单个时钟源并且分配给3DIC内的元件。 通过选择性可控制的触发器提供延迟到时钟路径，以帮助提供同步操作。 在某些实施例中，提供了3D触发器，其包括设置在3DIC的第一层中的主锁存器。 主锁存器被配置为接收触发器输入和时钟输入，主锁存器被配置为提供主锁存器输出。 3D触发器还包括设置在3DIC的至少一个附加层中的至少一个从锁存器，所述至少一个从锁存器被配置为提供3DIC触发器输出。 3D触发器还包括将主锁存器输出耦合到从锁存器的输入端（MIV）的至少一个单片间隔器。

公开(公告)号：US20140253196A1

公开(公告)日：2014-09-11

申请号：US13784915

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Yang Du ,  Jing Xie ,  Kambiz Samadi

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L27/0688 ,  H01L2924/0002 ,  H03K3/0372 ,  H01L2924/00

Abstract: Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is provided to clock paths by selectively controllable flip-flops to help provide synchronous operation. In certain embodiments, 3D flip-flop are provided that include a master latch disposed in a first tier of a 3DIC. The master latch is configured to receive a flip-flop input and a clock input, the master latch configured to provide a master latch output. The 3D flip-flop also includes at least one slave latch disposed in at least one additional tier of the 3DIC, the at least one slave latch configured to provide a 3DIC flip-flop output. The 3D flip-flop also includes at least one monolithic intertier via (MIV) coupling the master latch output to an input of the slave latch.

Abstract translation: 公开了一种单片三维（3D）集成电路（IC）（3DIC）和相关方法中的触发器。 在一个实施例中，为3DIC提供单个时钟源并且分配给3DIC内的元件。 通过选择性可控制的触发器提供延迟到时钟路径，以帮助提供同步操作。 在某些实施例中，提供了3D触发器，其包括设置在3DIC的第一层中的主锁存器。 主锁存器被配置为接收触发器输入和时钟输入，主锁存器被配置为提供主锁存器输出。 3D触发器还包括设置在3DIC的至少一个附加层中的至少一个从锁存器，所述至少一个从锁存器被配置为提供3DIC触发器输出。 3D触发器还包括将主锁存器输出耦合到从锁存器的输入端（MIV）的至少一个单片间隔器。

公开(公告)号：US20140131885A1

公开(公告)日：2014-05-15

申请号：US13753193

申请日：2013-01-29

Applicant: QUALCOMM INCORPORATED

Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Yang Du ,  Robert P. Gilmore

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/49827 ,  G06F17/5068 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract translation: 硬宏包括限定硬宏区域并具有顶部和底部以及从顶部到底部的宏宏厚度的周边，硬宏包括从顶部到底部延伸穿过硬宏厚度的多个通孔。 还有一种具有顶层，底层和至少一个中间层的集成电路，顶层包括顶层导电迹线，中间层包括硬宏，底层包括底层导电迹线，其中顶部 层导电迹线通过延伸穿过硬宏的通孔连接到底层导电迹线。

公开(公告)号：US10176147B2

公开(公告)日：2019-01-08

申请号：US15452299

申请日：2017-03-07

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Amin Ansari ,  Yang Du

IPC: G06F9/30 ,  G06F15/80 ,  H01L21/00 ,  H01L25/00 ,  H01L27/00 ,  G06F9/38 ,  G06F12/0875 ,  G06F15/76 ,  H01L21/822 ,  H01L25/065 ,  H01L27/06

Abstract: Multi-processor core three-dimensional (3D) integrated circuits (ICs) (3DICs) and related methods are disclosed. In aspects disclosed herein, ICs are provided that include a central processing unit (CPU) having multiple processor cores (“cores”) to improve performance. To further improve CPU performance, the multiple cores can also be designed to communicate with each other to offload workloads and/or share resources for parallel processing, but at a communication overhead associated with passing data through interconnects which have an associated latency. To mitigate this communication overhead inefficiency, aspects disclosed herein provide the CPU with its multiple cores in a 3DIC. Because 3DICs can overlap different IC tiers and/or align similar components in the same IC tier, the cores can be designed and located between or within different IC tiers in a 3DIC to reduce communication distance associated with processor core communication to share workload and/or resources, thus improving performance of the multi-processor CPU design.

公开(公告)号：US10121743B2

公开(公告)日：2018-11-06

申请号：US15472614

申请日：2017-03-29

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Kambiz Samadi ,  Jing Xie ,  Yang Du

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L25/065

Abstract: Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.