公开(公告)号：US20170038813A1

公开(公告)日：2017-02-09

申请号：US14819384

申请日：2015-08-05

Applicant: QUALCOMM INCORPORATED

Inventor： KRISHNA VSSSR VANKA ,  SRAVAN KUMAR AMBAPURAM

IPC: G06F1/32

CPC classification number: G06F1/32 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D50/20

Abstract: Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A core of the multi-core SoC entering an idle state is identified. For a low power mode of the core, an entry power cost of the core and an exit power cost of the core is calculated. A working set size for a cache associated with the core is also calculated. A latency for the cache to exit the low power mode of the core is calculated using the working set size. Finally, a determination is made whether the low power mode for the core results in a power savings over an active mode for the core based in part on the entry and exit power costs of the core, and the latency of the cache exiting the low power mode.

Abstract translation: 提出了一种用于改进多核片上系统芯片（SoC）中低功耗模式实现的系统和方法。 确定多核SoC进入空闲状态的核心。 对于核心的低功耗模式，计算核心的入口电力成本和核心的出口电力成本。 还计算与核心相关联的高速缓存的工作集大小。 使用工作集大小计算高速缓存退出核心低功耗模式的延迟。 最后，确定核心的低功耗模式是否能够部分地基于核心的进入和退出功率成本导致核心的主动模式的功率节省，以及高速缓存退出低功率的等待时间 模式。

公开(公告)号：US20160062438A1

公开(公告)日：2016-03-03

申请号：US14472295

申请日：2014-08-28

Applicant: QUALCOMM INCORPORATED

Inventor： ASUTOSH DAS ,  KRISHNA VSSSR VANKA ,  SRAVAN KUMAR AMBAPURAM ,  SUJIT REDDY THUMMA

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: Systems and methods that allow for dynamic quality of service (QoS) levels for an application processor in a multi-core on-chip system (SoC) in a portable computing device (PCD) are presented. During operation of the PCD an operational load of a co-processor of the SoC is determined, where the co-processor is in communication with an application processor of the SoC. Based on the determined load, the co-processor determines a QoS level required from the application processor. The QoS level is communicated to the application processor. The application processor determines whether it can implement power optimization measures, such as entering into a low power mode (LPM), based at least in part on the dynamically communicated QoS level from the co-processor. The present disclosure provides a cost effective ability to reduce power consumption in PCDs implementing one or more cores or CPUs that are dependent upon the application processor.

Abstract translation: 提出了允许在便携式计算设备（PCD）中的多核芯片系统（SoC）中的应用处理器的动态服务质量（QoS）级别的系统和方法。 在PCD的操作期间，确定SoC的协处理器的操作负载，其中协处理器与SoC的应用处理器通信。 基于确定的负载，协处理器确定从应用处理器所需的QoS等级。 QoS级别被传送到应用处理器。 应用处理器至少部分地基于来自协处理器的动态传达的QoS级别来确定它是否可以实现诸如进入低功率模式（LPM）的功率优化措施。 本公开提供了降低PCD实现依赖于应用处理器的一个或多个核心或CPU的功耗的成本有效的能力。

公开(公告)号：US20170038999A1

公开(公告)日：2017-02-09

申请号：US15234025

申请日：2016-08-11

Applicant: QUALCOMM INCORPORATED

Inventor： KRISHNA VSSSR VANKA ,  NARASIMHAN AGARAM ,  SRAVAN KUMAR AMBAPURAM

IPC: G06F3/06 ,  G06F12/0893 ,  G06F12/0804

CPC classification number: G06F3/0653 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0683 ,  G06F12/0804 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/60 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152

Abstract: Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A cache memory of the multi-core SoC not being accessed by other components of the SoC is identified and a number of dirty cache lines present in the cache memory is determined. For a low power mode of the core, an entry latency based on the number of dirty cache lines is determined, and an exit latency is determined. An entry power cost for the low power mode is also determined based on the number of dirty cache lines A determination is made whether the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost and the entry latency of the cache memory entering the first power mode.

Abstract translation: 提出了一种在多核片上系统（SoC）中改进低功耗模式实现的系统和方法。 识别未被SoC的其他组件访问的多核SoC的高速缓冲存储器，并且确定高速缓冲存储器中存在的多个脏高速缓存行。 对于核心的低功耗模式，确定基于脏高速缓存行数的入口延迟，并且确定退出延迟。 低功率模式的输入功率成本也根据脏高速缓存线的数量来确定。确定高速缓冲存储器的低功耗模式是否至少基于高速缓存存储器的活动模式的功率节省 进入电源成本和进入第一电源模式的高速缓冲存储器的进入延迟。

公开(公告)号：US20150261583A1

公开(公告)日：2015-09-17

申请号：US14210064

申请日：2014-03-13

Applicant: QUALCOMM INCORPORATED

Inventor： KRISHNA VSSSR VANKA ,  SHIRISH KUMAR AGARWAL ,  SRAVAN KUMAR AMBAPURAM

IPC: G06F9/54

CPC classification number: G06F9/54 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/544

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.

Abstract translation: 提供了允许处理器之间的动态时钟和电压调节（DCVS）感知处理器间通信的系统和方法，例如在便携式计算设备（“PCD”）中使用的处理器之间的处理器间通信。 在PCD的操作期间，在第一处理组件处接收至少一个数据分组。 此外，第一处理组件还接收关于在动态时钟和电压缩放（DCVS）下操作的第二处理组件的工作负载信息。 至少部分地基于所接收的工作负载信息，确定是否将所述至少一个数据分组从第一处理组件发送到第二处理组件或缓冲器，提供降低功耗的成本有效的能力，以及 提高了使用多核或多CPU实现DCVS算法或逻辑的PCD的电池寿命。

公开(公告)号：US20180067768A1

公开(公告)日：2018-03-08

申请号：US15257691

申请日：2016-09-06

Applicant: QUALCOMM INCORPORATED

Inventor： VAIBHAV BHALLA ,  KRISHNA VSSSR VANKA ,  MURALI DHULIPALA

IPC: G06F9/48

CPC classification number: G06F9/4893 ,  G06F1/203 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  Y02D10/122 ,  Y02D10/171

Abstract: Methods and systems for data path aware thermal management in a portable computing device (“PCD”) are disclosed. A trigger event may be received at a thermal module in the PCD. The thermal module also receives thermal information about a plurality of processing components of the PCD in response to the trigger event, the thermal information including a temperature at the locations of the plurality of processing components. The thermal module also receives thermal information about at least one subsystem in response to the trigger event, the thermal information including temperature modeling information about the at least one subsystem and a second temperature at the location of the at least one subsystem. A thermal impact from the plurality of processing components executing a task over a period of time is predicted and a determination is made which processing component has the smallest amount of thermal impact from executing the task.

公开(公告)号：US20160203083A1

公开(公告)日：2016-07-14

申请号：US14595998

申请日：2015-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： HEE JUN PARK ,  KRISHNA VSSSR VANKA ,  SRAVAN KUMAR AMBAPURAM ,  SHIRISH KUMAR AGARWAL ,  ASHVINKUMAR NAMJOSHI ,  HARSHAD BHUTADA

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F9/4856 ,  G06F9/5016 ,  G06F11/34 ,  G06F11/3433 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0842 ,  G06F2212/1021 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.

Abstract translation: 描述了多集群异构处理器架构中的动态缓存扩展。 一个实施例是包括具有第一级二（L2）高速缓存的第一处理器集群和具有第二L2高速缓存的第二处理器集群的系统。 该系统还包括与第一和第二L2高速缓存通信的控制器。 控制器从第一处理器集群接收处理器工作负载输入和高速缓存工作负载输入。 基于处理器工作负载输入和缓存工作负荷输入，高速缓存控制器确定与第一处理器集群相关联的当前任务是否受到第一L2高速缓存的大小阈值或第一处理器集群的性能阈值的限制。 如果当前任务受到第一L2高速缓存的大小阈值的限制，则控制器使用第二L2高速缓存的至少一部分作为第一L2高速缓存的扩展。

公开(公告)号：US20160124778A1

公开(公告)日：2016-05-05

申请号：US14993991

申请日：2016-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： KRISHNA VSSSR VANKA ,  SHIRISH KUMAR AGARWAL ,  SRAVAN KUMAR AMBAPURAM

IPC: G06F9/54 ,  G06F1/32

CPC classification number: G06F9/54 ,  G06F1/324 ,  G06F1/3296 ,  G06F9/544

Abstract: Systems and methods that allow for Dynamic Clock and Voltage Scaling (DCVS) aware interprocessor communications among processors such as those used in or with a portable computing device (“PCD”) are presented. During operation of the PCD at least one data packet is received at a first processing component. Additionally, the first processing component also receives workload information about a second processing component operating under dynamic clock and voltage scaling (DCVS). A determination is made, based at least in part on the received workload information, whether to send the at least one data packet from the first processing component to the second processing component or to a buffer, providing a cost effective ability to reduce power consumption and improved battery life in PCDs with multi-cores or multi-CPUs implementing DCVS algorithms or logic.