公开(公告)号：US20170038999A1

公开(公告)日：2017-02-09

申请号：US15234025

申请日：2016-08-11

Applicant: QUALCOMM INCORPORATED

Inventor： KRISHNA VSSSR VANKA ,  NARASIMHAN AGARAM ,  SRAVAN KUMAR AMBAPURAM

IPC: G06F3/06 ,  G06F12/0893 ,  G06F12/0804

CPC classification number: G06F3/0653 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0683 ,  G06F12/0804 ,  G06F12/0893 ,  G06F2212/1028 ,  G06F2212/60 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/152

Abstract: Systems and methods for improved implementation of low power modes in a multi-core system-on-a-chip (SoC) are presented. A cache memory of the multi-core SoC not being accessed by other components of the SoC is identified and a number of dirty cache lines present in the cache memory is determined. For a low power mode of the core, an entry latency based on the number of dirty cache lines is determined, and an exit latency is determined. An entry power cost for the low power mode is also determined based on the number of dirty cache lines A determination is made whether the low power mode for the cache memory results in a power savings over an active mode for the cache memory based at least on the entry power cost and the entry latency of the cache memory entering the first power mode.

Abstract translation: 提出了一种在多核片上系统（SoC）中改进低功耗模式实现的系统和方法。 识别未被SoC的其他组件访问的多核SoC的高速缓冲存储器，并且确定高速缓冲存储器中存在的多个脏高速缓存行。 对于核心的低功耗模式，确定基于脏高速缓存行数的入口延迟，并且确定退出延迟。 低功率模式的输入功率成本也根据脏高速缓存线的数量来确定。确定高速缓冲存储器的低功耗模式是否至少基于高速缓存存储器的活动模式的功率节省 进入电源成本和进入第一电源模式的高速缓冲存储器的进入延迟。