公开(公告)号：US20200066852A1

公开(公告)日：2020-02-27

申请号：US16670805

申请日：2019-10-31

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Kazuma YOSHIDA ,  Takeshi IMAMURA ,  Toshikazu IMAI ,  Ryosuke OKAWA ,  Ryou KATO

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L23/00 ,  H01L21/8234 ,  H01L27/02

Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

公开(公告)号：US20190319126A1

公开(公告)日：2019-10-17

申请号：US16447100

申请日：2019-06-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshihiro MATSUSHIMA ,  Shigetoshi SOTA ,  Eiji YASUDA ,  Toshikazu IMAI ,  Ryosuke OKAWA ,  Kazuma YOSHIDA ,  Ryou KATO

IPC: H01L29/78 ,  H01L27/088 ,  H01L23/15

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 μm, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

公开(公告)号：US20180122939A1

公开(公告)日：2018-05-03

申请号：US15854220

申请日：2017-12-26

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tomonari OTA ,  Shigetoshi SOTA ,  Eiji YASUDA ,  Takeshi IMAMURA ,  Toshikazu IMAI ,  Ryosuke OKAWA ,  Kazuma YOSHIDA ,  Masaaki HIRAKO ,  Dohwan AHN

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L21/823475 ,  H01L21/823487 ,  H01L24/47 ,  H01L27/088 ,  H01L29/41741 ,  H01L29/4238

Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.

公开(公告)号：US20190229194A1

公开(公告)日：2019-07-25

申请号：US16146272

申请日：2018-09-28

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Kazuma YOSHIDA ,  Takeshi IMAMURA ,  Toshikazu IMAI ,  Ryosuke OKAWA ,  Ryou KATO

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L23/00

Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.

公开(公告)号：US20190273141A1

公开(公告)日：2019-09-05

申请号：US16418617

申请日：2019-05-21

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Kazuma YOSHIDA ,  Takeshi IMAMURA ,  Toshikazu IMAI ,  Ryosuke OKAWA ,  Ryou KATO

IPC: H01L29/417 ,  H01L29/78 ,  H01L27/088 ,  H01L23/00 ,  H01L29/423

Abstract: A semiconductor device includes a first gate electrode, a plurality of first source electrodes, a second gate electrode, and a plurality of second source electrodes. The first gate electrode is arranged with no other electrode between the first gate electrode and a first short side of the semiconductor substrate. The plurality of first source electrodes include a plurality of approximately rectangular first source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate. The second gate electrode is arranged with no other electrode between the second gate electrode and a second short side of the semiconductor substrate. The plurality of second source electrodes include a plurality of approximately rectangular second source electrodes arranged in stripes extending parallel to the lengthwise direction of the semiconductor substrate.