公开(公告)号：US20190319126A1

公开(公告)日：2019-10-17

申请号：US16447100

申请日：2019-06-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshihiro MATSUSHIMA ,  Shigetoshi SOTA ,  Eiji YASUDA ,  Toshikazu IMAI ,  Ryosuke OKAWA ,  Kazuma YOSHIDA ,  Ryou KATO

IPC: H01L29/78 ,  H01L27/088 ,  H01L23/15

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 μm, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.

公开(公告)号：US20180122939A1

公开(公告)日：2018-05-03

申请号：US15854220

申请日：2017-12-26

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Tomonari OTA ,  Shigetoshi SOTA ,  Eiji YASUDA ,  Takeshi IMAMURA ,  Toshikazu IMAI ,  Ryosuke OKAWA ,  Kazuma YOSHIDA ,  Masaaki HIRAKO ,  Dohwan AHN

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L21/823475 ,  H01L21/823487 ,  H01L24/47 ,  H01L27/088 ,  H01L29/41741 ,  H01L29/4238

Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.