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公开(公告)号：US10270448B1
公开(公告)日：2019-04-23
申请号：US15980882
申请日：2018-05-16
Applicant: NXP B.V.
Inventor： Kristof Blutman , Sebastien Antonius Josephus Fabrie , Juan Diego Echeverri Escobar , Ajay Kapoor , Jose de Jesus Pineda de Gyvez , Hamed Fatemi
IPC: H03K19/0185
Abstract: A level shifter circuit is described herein for shifting a signal from a first voltage domain to a second voltage domain. The level shifter circuit includes two current paths between a supply terminal of the first voltage domain and a supply terminal of the second voltage domain. The first and second current paths each include a differential transistor that receives a signal from a pulse generator in a first voltage domain. The pulse generator provides pulses to the differential transistors based on an input signal to be translated to the second voltage domain. The level shifter includes a latch circuit in the second voltage domain that includes two inputs where each input is biased at a node of one of the current paths. Each current path includes a bias transistor whose control terminal receives a compensated biasing voltage for biasing the bias transistor. The compensated biasing voltage is compensated to account for drive strength variation of at least one transistor in each current path.
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公开(公告)号：US10739846B2
公开(公告)日：2020-08-11
申请号：US16215780
申请日：2018-12-11
Applicant: NXP B.V.
Inventor： Ajay Kapoor , Juan Diego Echeverri Escobar , Kristof Blutman , Sebastien Antonius Josephus Fabrie , Jose de Jesus Pineda de Gyvez , Hamed Fatemi
IPC: H03L5/00 , G06F1/3296 , H03K3/03
Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.
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公开(公告)号：US20170012611A1
公开(公告)日：2017-01-12
申请号：US14792276
申请日：2015-07-06
Applicant: NXP B.V.
Inventor： Juan Echeverri Escobar , Jose de Jesus Pineda de Gyvez , Sebastien Antonius Josephus Fabrie
IPC: H03K3/037
CPC classification number: H03K3/0372 , H03K3/012 , H03K3/037 , H03K19/0016
Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.
Abstract translation: 公开了一种装置和方法的实施例。 在一个实施例中，公开了一种触发器电路。 触发器电路包括主锁存器，连接到主锁存器的从锁存器以及连接在主锁存器和从锁存器之间并被配置为执行状态保持和双重采样的双功能电路。
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Patent Agency Ranking
公开(公告)号：US10819331B1
公开(公告)日：2020-10-27
申请号：US16404931
申请日：2019-05-07
Applicant: NXP B.V.
Inventor： Sebastien Antonius Josephus Fabrie , Maarten Vertregt , Ajay Kapoor
IPC: H03K17/687 , H03K17/14 , H03K17/16
Abstract: Self-regulating body-biasing techniques for Process, Voltage, and Temperature (PVT) fluctuation compensation in Fully-Depleted Silicon-on-Insulator (FDSOI) semiconductors are disclosed. In an illustrative, non-limiting embodiment, an electronic device may include a logic cell having a plurality of FDSOI transistors manufactured thereon; and at least one current source coupled to a body terminal of each transistor in a subset of the FDSOI transistors, wherein the current source is configured to output a high-impedance current.
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公开(公告)号：US20170017486A1
公开(公告)日：2017-01-19
申请号：US14800952
申请日：2015-07-16
Applicant: NXP B.V.
IPC: G06F9/30
CPC classification number: G06F9/3005 , G06F9/30098 , G06F9/30123 , G06F9/30134 , G06F9/30181 , G06F9/327 , G06F9/3836 , G06F9/3857 , G06F9/3867 , G06F9/3885
Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.
Abstract translation: 在一个实施例中，公开了一种用于处理微控制器中的指令的方法。 在本实施例中，该方法涉及在执行指令时接收到中断，完成阴影功能单元完成指令的执行，并且在服务中断时终止重新执行指令并更新主寄存器文件 由阴影功能单元执行指令的结果。
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公开(公告)号：US10942748B2
公开(公告)日：2021-03-09
申请号：US14800952
申请日：2015-07-16
Applicant: NXP B.V.
Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.
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公开(公告)号：US20200183486A1
公开(公告)日：2020-06-11
申请号：US16215780
申请日：2018-12-11
Applicant: NXP B.V.
Inventor： Ajay Kapoor , Juan Diego Echeverri Escobar , Kristof Blutman , Sebastien Antonius Josephus Fabrie , Jose de Jesus Pineda de Gyvez , Hamed Fatemi
IPC: G06F1/3296 , H03K3/03
Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.
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公开(公告)号：US09634649B2
公开(公告)日：2017-04-25
申请号：US14792276
申请日：2015-07-06
Applicant: NXP B.V.
Inventor： Juan Echeverri Escobar , Jose de Jesus Pineda de Gyvez , Sebastien Antonius Josephus Fabrie
CPC classification number: H03K3/0372 , H03K3/012 , H03K3/037 , H03K19/0016
Abstract: Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling.
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