公开(公告)号：US09664737B2

公开(公告)日：2017-05-30

申请号：US14812219

申请日：2015-07-29

Applicant: MediaTek Inc.

Inventor： Kok-Tiong Tee ,  Heng-Meng Liu ,  Yipin Wu

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/30

CPC classification number: G01R31/31725 ,  G01R31/3016

Abstract: A method for providing an on-chip variation determination and an integrated circuit utilizing the same are provided. The method includes: outputting, by a launch register circuit, a test data to the capture register circuit according to the first clock; receiving, by a capture register circuit, the test data from the launch register circuit according to the second clock; adjusting, by a control circuit, a first number of a first chain of delay elements to generate the first clock and a second number of a second chain of delay elements for the capture register circuit to just capture the test data to generate the second clock; and determining, by the control circuit, a path delay between the launch register circuit and the capture register circuit based on the first number of the first chain of delay elements and the second number of the second chain of delay elements.

公开(公告)号：US20160065182A1

公开(公告)日：2016-03-03

申请号：US14468345

申请日：2014-08-26

Applicant: MEDIATEK INC.

Inventor： Yuan-Hung Chung ,  Jiunn-Nan Hwang ,  Yipin Wu ,  Tsung-Ying Tsai ,  Chin-Wei Huang

IPC: H03K3/012 ,  H03K17/687

CPC classification number: H03K17/687 ,  H03H11/0422 ,  H03K17/164 ,  H03K19/00346

Abstract: A digital circuit comprises a plurality of functional circuits and a finite state machine. Each functional circuit comprises a digital macro, a resistance control device and at least one device with capacitance. The digital macro is coupled to a ground. The resistance control device is electrically connected between the digital macro and an always-on power mesh. The at least one device with capacitance is electrically connected between the resistance control device and the ground. The finite state machine is electrically connected to the resistance control device, and is configured to adjust the resistance of the resistance control device.

Abstract translation: 数字电路包括多个功能电路和有限状态机。 每个功能电路包括数字宏，电阻控制装置和至少一个具有电容的装置。 数字宏耦合到地面。 电阻控制装置电连接在数字宏和永久在线功率网之间。 具有电容的至少一个装置电连接在电阻控制装置和地之间。 有限状态机电连接到电阻控制装置，并且被配置为调整电阻控制装置的电阻。

公开(公告)号：US09543943B2

公开(公告)日：2017-01-10

申请号：US14468345

申请日：2014-08-26

Applicant: MEDIATEK INC.

Inventor： Yuan-Hung Chung ,  Jiunn-Nan Hwang ,  Yipin Wu ,  Tsung-Ying Tsai ,  Chin-Wei Huang

IPC: H03K5/00 ,  H03K17/687 ,  H03K19/003 ,  H03K17/16 ,  H03H11/04

CPC classification number: H03K17/687 ,  H03H11/0422 ,  H03K17/164 ,  H03K19/00346

Abstract: A digital circuit comprises a plurality of functional circuits and a finite state machine. Each functional circuit comprises a digital macro, a resistance control device and at least one device with capacitance. The digital macro is coupled to a ground. The resistance control device is electrically connected between the digital macro and an always-on power mesh. The at least one device with capacitance is electrically connected between the resistance control device and the ground. The finite state machine is electrically connected to the resistance control device, and is configured to adjust the resistance of the resistance control device.

Abstract translation: 数字电路包括多个功能电路和有限状态机。 每个功能电路包括数字宏，电阻控制装置和至少一个具有电容的装置。 数字宏耦合到地面。 电阻控制装置电连接在数字宏和永久在线功率网之间。 具有电容的至少一个装置电连接在电阻控制装置和地之间。 有限状态机电连接到电阻控制装置，并且被配置为调整电阻控制装置的电阻。