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公开(公告)号：US09876517B2
公开(公告)日：2018-01-23
申请号：US14754860
申请日：2015-06-30
Applicant: MEDIATEK Inc.
Inventor： Sheng-Hong Yan , Sheng-Hao Chen , Paul Cheng Po Liang , Jen-Che Tsai
CPC classification number: H04B1/1081 , H04B1/10 , H04B1/123 , H04B17/11
Abstract: A radio frequency (RF) receiver includes a digital tuning engine; and I-path and Q-path analog filters, tuned by the digital tuning engine. The digital tuning engine gets an I/Q imbalance difference, and the digital tuning engines tunes the I-path analog filter and/or the Q-path analog filter based on the I/O imbalance difference.
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公开(公告)号：US09385740B2
公开(公告)日：2016-07-05
申请号：US14919830
申请日：2015-10-22
Applicant: MEDIATEK Inc.
Inventor： Chi Yun Wang , Jen-Che Tsai , Shu-Wei Chu
CPC classification number: H03M1/462 , H03M1/0854 , H03M1/12 , H03M1/1245 , H03M1/38 , H03M1/403 , H03M1/42 , H03M1/466 , H03M1/468 , H03M3/37 , H03M3/458
Abstract: A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.
Abstract translation: 提供了包括比较器，输入开关单元，正转换电容器阵列，负转换电容器阵列和SAR控制器的SAR ADC。 输入开关单元将差分模拟输入信号交替耦合到比较器。 正和负转换电容器阵列在采样阶段对差分模拟输入信号进行采样。 SAR控制器在采样阶段结束时复位电容器阵列中的开关，将采样电压改变为残余信号，产生一个中间数字代码，根据比较器的输出在转换阶段控制开关，以转换 到中间数字码的残留信号，根据中间数字码产生数字码，并在转换阶段结束时使用反相中间数字码来控制开关。
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公开(公告)号：US20160134300A1
公开(公告)日：2016-05-12
申请号：US14919830
申请日：2015-10-22
Applicant: MEDIATEK Inc.
Inventor： Chi Yun Wang , Jen-Che Tsai , SHU-WEI CHU
CPC classification number: H03M1/462 , H03M1/0854 , H03M1/12 , H03M1/1245 , H03M1/38 , H03M1/403 , H03M1/42 , H03M1/466 , H03M1/468 , H03M3/37 , H03M3/458
Abstract: A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.
Abstract translation: 提供了包括比较器，输入开关单元，正转换电容器阵列，负转换电容器阵列和SAR控制器的SAR ADC。 输入开关单元将差分模拟输入信号交替耦合到比较器。 正和负转换电容器阵列在采样阶段对差分模拟输入信号进行采样。 SAR控制器在采样阶段结束时复位电容器阵列中的开关，将采样电压改变为残余信号，产生一个中间数字代码，根据比较器的输出在转换阶段控制开关，以转换 到中间数字码的残留信号，根据中间数字码产生数字码，并在转换阶段结束时使用反相中间数字码来控制开关。
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Patent Agency Ranking
公开(公告)号：US20130266102A1
公开(公告)日：2013-10-10
申请号：US13798241
申请日：2013-03-13
Applicant: MEDIATEK INC.
Inventor： Sheng-Hong Yan , Sheng-Hao Chen , Cheng-Po Liang , Jen-Che Tsai
IPC: H04B1/10
CPC classification number: H04B1/1081 , H04B1/10 , H04B1/123 , H04B17/11
Abstract: A radio frequency (RF) receiver includes a digital tuning engine; I-path and Q-path analog filters, tuned by the digital tuning engine; and a digital compensation circuit. The digital tuning engine executes a RC (resistor-capacitor) time constant calibration to adjust respective cut-off frequencies of the I-path analog filter and the Q-path analog filter. The digital tuning engine executes a filter mismatch calibration to match the I-path analog filter and the Q-path analog filter. The digital tuning engine executes a filter residual mismatch calibration to match an I-path response from the I-path analog filter to the digital compensation circuit and a Q-path response from the Q-path analog filter to the digital compensation circuit.
Abstract translation: 射频（RF）接收机包括数字调谐引擎; I路径和Q路径模拟滤波器，由数字调谐引擎调谐; 和数字补偿电路。 数字调谐引擎执行RC（电阻 - 电容）时间常数校准，以调整I路径模拟滤波器和Q路径模拟滤波器的相应截止频率。 数字调谐引擎执行滤波器失配校准，以匹配I路径模拟滤波器和Q路径模拟滤波器。 数字调谐引擎执行滤波器残余失配校准，以匹配从I路径模拟滤波器到数字补偿电路的I路径响应以及从Q路径模拟滤波器到数字补偿电路的Q路径响应。
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5.发明申请公开(公告)号：US20150123830A1
公开(公告)日：2015-05-07
申请号：US14483137
申请日：2014-09-10
Applicant: MEDIATEK INC.
Inventor： Sheng-Hao Chen , Yen-Chuan Huang , Min-Hua Wu , Chun-Hao Liao , Hung-Pin Ma , Tzu-Hao Yu , Jen-Che Tsai
CPC classification number: H03M1/0626 , H03M1/66 , H03M1/74 , H03M9/00
Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.
Abstract translation: 一种数模转换系统，包括：第一数据转换电路，用于接收以第一时钟频率发送的第一数字数据流，用于将第一数字数据流转换为在第二时钟发送的多个第二数字数据流 并且用于并行地输出第二数字数据流; 第二数据转换电路，用于从第一数据转换电路接收第二数字数据流，并将第二数字数据流转换成以第三时钟频率发送的第三数字数据流; 以及第一数模转换器，用于将第三数字数据流转换为第一输出模拟数据流。 第二个时钟频率低于第一个时钟频率和第三个时钟频率。
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公开(公告)号：US20150303957A1
公开(公告)日：2015-10-22
申请号：US14754860
申请日：2015-06-30
Applicant: MEDIATEK Inc.
Inventor： Sheng-Hong Yan , Sheng-Hao Chen , Paul Cheng Po Liang , Jen-Che Tsai
CPC classification number: H04B1/1081 , H04B1/10 , H04B1/123 , H04B17/11
Abstract: A radio frequency (RF) receiver includes a digital tuning engine; and I-path and Q-path analog filters, tuned by the digital tuning engine. The digital tuning engine gets an I/Q imbalance difference, and the digital tuning engines tunes the I-path analog filter and/or the Q-path analog filter based on the I/Q imbalance difference.
Abstract translation: 射频（RF）接收机包括数字调谐引擎; 以及由数字调谐引擎调谐的I-path和Q-path模拟滤波器。 数字调谐引擎获得I / Q不平衡差异，数字调谐引擎根据I / Q不平衡差调谐I路模拟滤波器和/或Q路径模拟滤波器。
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7.发明授权公开(公告)号：US09100078B2
公开(公告)日：2015-08-04
申请号：US13798241
申请日：2013-03-13
Applicant: MEDIATEK Inc.
Inventor： Sheng-Hong Yan , Sheng-Hao Chen , Paul Cheng Po Liang , Jen-Che Tsai
CPC classification number: H04B1/1081 , H04B1/10 , H04B1/123 , H04B17/11
Abstract: A radio frequency (RF) receiver includes a digital tuning engine; I-path and Q-path analog filters, tuned by the digital tuning engine; and a digital compensation circuit. The digital tuning engine executes a RC (resistor-capacitor) time constant calibration to adjust respective cut-off frequencies of the I-path analog filter and the Q-path analog filter. The digital tuning engine executes a filter mismatch calibration to match the I-path analog filter and the Q-path analog filter. The digital tuning engine executes a filter residual mismatch calibration to match an I-path response from the I-path analog filter to the digital compensation circuit and a Q-path response from the Q-path analog filter to the digital compensation circuit.
Abstract translation: 射频（RF）接收机包括数字调谐引擎; I路径和Q路径模拟滤波器，由数字调谐引擎调谐; 和数字补偿电路。 数字调谐引擎执行RC（电阻 - 电容）时间常数校准，以调整I路径模拟滤波器和Q路径模拟滤波器的相应截止频率。 数字调谐引擎执行滤波器失配校准，以匹配I路径模拟滤波器和Q路径模拟滤波器。 数字调谐引擎执行滤波器残余失配校准，以匹配从I路径模拟滤波器到数字补偿电路的I路径响应以及从Q路径模拟滤波器到数字补偿电路的Q路径响应。
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8.发明授权公开(公告)号：US09094034B2
公开(公告)日：2015-07-28
申请号：US14483137
申请日：2014-09-10
Applicant: MEDIATEK INC.
Inventor： Sheng-Hao Chen , Yen-Chuan Huang , Min-Hua Wu , Chun-Hao Liao , Hung-Pin Ma , Tzu-Hao Yu , Jen-Che Tsai
CPC classification number: H03M1/0626 , H03M1/66 , H03M1/74 , H03M9/00
Abstract: A digital to analog converting system, which comprises: a first data converting circuit, for receiving a first digital data stream transmitted at a first clock frequency, for converting the first digital data stream to a plurality of second digital data streams transmitted at a second clock frequency, and for outputting the second digital data streams in parallel; a second data converting circuit, for receiving the second digital data streams from the first data converting circuit, and for converting the second digital data streams to a third digital data stream transmitted at a third clock frequency; and a first digital to analog converter, for converting the third digital data stream to a first output analog data stream. The second clock frequency is lower than the first clock frequency and the third clock frequency.
Abstract translation: 一种数模转换系统，包括：第一数据转换电路，用于接收以第一时钟频率发送的第一数字数据流，用于将第一数字数据流转换为在第二时钟发送的多个第二数字数据流 并且用于并行地输出第二数字数据流; 第二数据转换电路，用于从第一数据转换电路接收第二数字数据流，并将第二数字数据流转换成以第三时钟频率发送的第三数字数据流; 以及第一数模转换器，用于将第三数字数据流转换为第一输出模拟数据流。 第二个时钟频率低于第一个时钟频率和第三个时钟频率。
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