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公开(公告)号：US09184730B2
公开(公告)日：2015-11-10
申请号：US14138557
申请日：2013-12-23
Applicant: MediaTek Inc.
Inventor： Chi Yun Wang , Chih-Hong Lou
CPC classification number: H03H11/1217 , H05B33/0845 , H05B33/0854 , H05B37/0218 , Y02B20/46
Abstract: A dynamic feed-forward OPAMP-based circuit is provided. A first amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. A second amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is coupled to a non-inverting input terminal of the first amplifying stage. A second capacitor is coupled to an inverting input terminal of the first amplifying stage. A feed-forward transconductance stage is coupled between the first and second capacitors and the second amplifying stage. The first and second capacitors and the feed-forward stage form a high-frequency path with a first gain curve, and the first amplifying stage and the second amplifying stage form a high-gain path with a second gain curve. The operational amplifier provides an open-loop gain according to the first and second gain curves.
Abstract translation: 提供了基于动态前馈OPAMP的电路。 第一放大级放大一对输入差分信号以提供一对中间差分信号。 第二放大级放大该对中间差分信号以提供一对输出差分信号。 第一电容器耦合到第一放大级的非反相输入端。 第二电容器耦合到第一放大级的反相输入端。 前馈跨导级耦合在第一和第二电容器与第二放大级之间。 第一和第二电容器和前馈级形成具有第一增益曲线的高频路径，并且第一放大级和第二放大级形成具有第二增益曲线的高增益路径。 运算放大器根据第一和第二增益曲线提供开环增益。
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公开(公告)号：US09385740B2
公开(公告)日：2016-07-05
申请号：US14919830
申请日：2015-10-22
Applicant: MEDIATEK Inc.
Inventor： Chi Yun Wang , Jen-Che Tsai , Shu-Wei Chu
CPC classification number: H03M1/462 , H03M1/0854 , H03M1/12 , H03M1/1245 , H03M1/38 , H03M1/403 , H03M1/42 , H03M1/466 , H03M1/468 , H03M3/37 , H03M3/458
Abstract: A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.
Abstract translation: 提供了包括比较器，输入开关单元，正转换电容器阵列，负转换电容器阵列和SAR控制器的SAR ADC。 输入开关单元将差分模拟输入信号交替耦合到比较器。 正和负转换电容器阵列在采样阶段对差分模拟输入信号进行采样。 SAR控制器在采样阶段结束时复位电容器阵列中的开关，将采样电压改变为残余信号，产生一个中间数字代码，根据比较器的输出在转换阶段控制开关，以转换 到中间数字码的残留信号，根据中间数字码产生数字码，并在转换阶段结束时使用反相中间数字码来控制开关。
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公开(公告)号：US20160134300A1
公开(公告)日：2016-05-12
申请号：US14919830
申请日：2015-10-22
Applicant: MEDIATEK Inc.
Inventor： Chi Yun Wang , Jen-Che Tsai , SHU-WEI CHU
CPC classification number: H03M1/462 , H03M1/0854 , H03M1/12 , H03M1/1245 , H03M1/38 , H03M1/403 , H03M1/42 , H03M1/466 , H03M1/468 , H03M3/37 , H03M3/458
Abstract: A SAR ADC including a comparator, an input switch unit, a positive conversion capacitor array, a negative conversion capacitor array, and a SAR controller is provided. The input switch unit alternately couples and decouples a differential analog input signal to the comparator. The positive and negative conversion capacitor arrays sample the differential analog input signal during the sampling phase. The SAR controller resets the switches in the capacitor arrays at the end of the sampling phase to change the sampled voltage into a residual signal, generates an intermediate digital code to control the switches during the conversion phase according to an output of the comparator to convert the residual signal to the intermediate digital code, generates the digital code according to the intermediate digital code, and uses an inverted intermediate digital code to control the switches at the end of the conversion phase.
Abstract translation: 提供了包括比较器，输入开关单元，正转换电容器阵列，负转换电容器阵列和SAR控制器的SAR ADC。 输入开关单元将差分模拟输入信号交替耦合到比较器。 正和负转换电容器阵列在采样阶段对差分模拟输入信号进行采样。 SAR控制器在采样阶段结束时复位电容器阵列中的开关，将采样电压改变为残余信号，产生一个中间数字代码，根据比较器的输出在转换阶段控制开关，以转换 到中间数字码的残留信号，根据中间数字码产生数字码，并在转换阶段结束时使用反相中间数字码来控制开关。
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公开(公告)号：US09263995B2
公开(公告)日：2016-02-16
申请号：US14073148
申请日：2013-11-06
Applicant: MediaTek Inc.
Inventor： Chi Yun Wang , Chih-Hong Lou
CPC classification number: H03F1/34 , H03F1/14 , H03F1/486 , H03F3/45475 , H03F3/45941 , H03F3/45946 , H03F2203/45138 , H03F2203/45512 , H03F2203/45514 , H03F2203/45576 , H03F2203/45644
Abstract: A multi-mode OPAMP-based circuit is provided. An input amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. An output amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is disposed in a first negative feedback loop of the output amplifying stage. A second capacitor is disposed in a second negative feedback loop of the output amplifying stage. A third capacitor is selectively disposed in a first positive feedback loop of the output amplifying stage or coupled to the first capacitor in parallel according to a control signal. A fourth capacitor is selectively disposed in a second positive feedback loop of the output amplifying stage or coupled to the second capacitor in parallel according to the control signal.
Abstract translation: 提供了基于多模式OPAMP的电路。 输入放大级放大一对输入差分信号以提供一对中间差分信号。 输出放大级放大一对中间差分信号以提供一对输出差分信号。 第一电容器设置在输出放大级的第一负反馈回路中。 第二电容器设置在输出放大级的第二负反馈回路中。 第三电容器选择性地设置在输出放大级的第一正反馈环路中，或者根据控制信号并联耦合到第一电容器。 第四电容器选择性地设置在输出放大级的第二正反馈环路中，或者根据控制信号并联耦合到第二电容器。
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