公开(公告)号：US20210195207A1

公开(公告)日：2021-06-24

申请号：US17190409

申请日：2021-03-03

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Tung-Hsing Wu ,  Yi-Hsin Huang ,  Lien-Fei Chen ,  Ting-An Lin ,  Han-Liang Chou

IPC: H04N19/15 ,  H04N19/105 ,  H04N19/172 ,  H04N19/159 ,  H04N19/184 ,  H04N19/463

Abstract: A video encoding apparatus includes a data buffer and a video encoding circuit. Encoding of a first frame includes: deriving reference pixels of a reference frame from reconstructed pixels of the first frame, respectively, and storing reference pixel data into the data buffer for inter prediction, wherein the reference pixel data include information of pixel values of the reference pixels. Encoding of a second frame includes performing prediction upon a coding unit in the second frame to determine a target predictor for the coding unit. The prediction performed upon the coding unit includes: determining the target predictor for the coding unit according to whether a search range on the reference frame for finding a predictor of the coding unit under an inter prediction mode includes at least one reference pixel of the reference frame that is not accessible to the video encoding circuit.

公开(公告)号：US10904577B2

公开(公告)日：2021-01-26

申请号：US16194396

申请日：2018-11-19

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Chung-Hua Tsai ,  Tung-Hsing Wu ,  Lien-Fei Chen ,  Yu-Kun Lin ,  Yi-Hsin Huang ,  Han-Liang Chou

IPC: H04N19/184 ,  H04N19/85 ,  H04N19/70

Abstract: A video compression system includes a video encoder and a bitstream processing circuit. The video encoder is hardware that performs hardware video encoding upon frames to generate a first bitstream. The first bitstream is output from an entropy encoding circuit of the video encoder. The bitstream processing circuit performs a bitstream post-processing operation upon the first bitstream to produce a second bitstream that is different from the first bitstream, and outputs the second bitstream as a compression output of the frames.

公开(公告)号：US20180027240A1

公开(公告)日：2018-01-25

申请号：US15653550

申请日：2017-07-19

Applicant: MEDIATEK INC.

Inventor： Yen-Chao Huang ,  Li-Heng Chen ,  Tung-Hsing Wu ,  Chung-Hua Tsai ,  Lien-Fei Chen ,  Han-Liang Chou

IPC: H04N19/159 ,  H04N19/50 ,  H04N19/176 ,  H04N19/61

CPC classification number: H04N19/159 ,  H04N19/174 ,  H04N19/176 ,  H04N19/436 ,  H04N19/50 ,  H04N19/61 ,  H04N19/91

Abstract: A video encoding apparatus has a bitstream buffer and a first video encoder. The first video encoder sequentially encodes coding blocks of a first video frame segment in a first encoding order, and outputs encoded data of the coding blocks of the first video frame segment to the bitstream buffer. The first video frame segment is partitioned into a plurality of column tiles, each having at least one tile. The first encoding order is identical to an encoding order of encoding a video frame segment with only a single column tile.

公开(公告)号：US20190007680A1

公开(公告)日：2019-01-03

申请号：US16004419

申请日：2018-06-10

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Lien-Fei Chen ,  Tung-Hsing Wu ,  Han-Liang Chou

IPC: H04N19/119 ,  H04N19/174 ,  H04N19/159 ,  H04N19/184 ,  H04N19/147 ,  H04N19/91 ,  H04N19/436

Abstract: A video encoder includes a video encoding circuit and a slice decision circuit. The video encoding circuit encodes a first slice in a frame according to a first coding unit boundary between an end of the first slice and a start of a second slice in the frame, and outputs a first bitstream of the first slice. The slice decision circuit predicts the first coding unit boundary before a bitstream of a last coding unit of the first slice is generated by the video encoding circuit, and informs the video encoding circuit of the first coding unit boundary. The video encoding circuit refers to the first coding unit boundary predicted by the slice decision circuit to ensure that a bitstream size of the first bitstream is constrained by a predetermined bitstream size threshold.

公开(公告)号：US11166029B2

公开(公告)日：2021-11-02

申请号：US17190409

申请日：2021-03-03

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Tung-Hsing Wu ,  Yi-Hsin Huang ,  Lien-Fei Chen ,  Ting-An Lin ,  Han-Liang Chou

IPC: H04N19/15 ,  H04N19/105 ,  H04N19/184 ,  H04N19/463 ,  H04N19/172 ,  H04N19/159

Abstract: A video encoding apparatus includes a data buffer and a video encoding circuit. Encoding of a first frame includes: deriving reference pixels of a reference frame from reconstructed pixels of the first frame, respectively, and storing reference pixel data into the data buffer for inter prediction, wherein the reference pixel data include information of pixel values of the reference pixels. Encoding of a second frame includes performing prediction upon a coding unit in the second frame to determine a target predictor for the coding unit. The prediction performed upon the coding unit includes: determining the target predictor for the coding unit according to whether a search range on the reference frame for finding a predictor of the coding unit under an inter prediction mode includes at least one reference pixel of the reference frame that is not accessible to the video encoding circuit.

公开(公告)号：US10972738B2

公开(公告)日：2021-04-06

申请号：US16367237

申请日：2019-03-27

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Tung-Hsing Wu ,  Yi-Hsin Huang ,  Lien-Fei Chen ,  Ting-An Lin ,  Han-Liang Chou

IPC: H04N19/159 ,  H04N19/15 ,  H04N19/105 ,  H04N19/172 ,  H04N19/184 ,  H04N19/463

Abstract: A video encoding apparatus includes a data buffer and a video encoding circuit. Encoding of a first frame includes: deriving reference pixels of a reference frame from reconstructed pixels of the first frame, respectively, and storing reference pixel data into the data buffer for inter prediction, wherein the reference pixel data include information of pixel values of the reference pixels. Encoding of a second frame includes performing prediction upon a coding unit in the second frame to determine a target predictor for the coding unit. The prediction performed upon the coding unit includes: checking if a search range on the reference frame for finding a predictor of the coding unit under an inter prediction mode includes at least one reference pixel of the reference frame that is not accessible to the video encoding circuit, and determining the target predictor for the coding unit according to a checking result.

公开(公告)号：US20190306510A1

公开(公告)日：2019-10-03

申请号：US16367237

申请日：2019-03-27

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Tung-Hsing Wu ,  Yi-Hsin Huang ,  Lien-Fei Chen ,  Ting-An Lin ,  Han-Liang Chou

IPC: H04N19/15 ,  H04N19/105 ,  H04N19/463 ,  H04N19/159 ,  H04N19/184 ,  H04N19/172

Abstract: A video encoding apparatus includes a data buffer and a video encoding circuit. Encoding of a first frame includes: deriving reference pixels of a reference frame from reconstructed pixels of the first frame, respectively, and storing reference pixel data into the data buffer for inter prediction, wherein the reference pixel data include information of pixel values of the reference pixels. Encoding of a second frame includes performing prediction upon a coding unit in the second frame to determine a target predictor for the coding unit. The prediction performed upon the coding unit includes: checking if a search range on the reference frame for finding a predictor of the coding unit under an inter prediction mode includes at least one reference pixel of the reference frame that is not accessible to the video encoding circuit, and determining the target predictor for the coding unit according to a checking result.

公开(公告)号：US20190246144A1

公开(公告)日：2019-08-08

申请号：US16194396

申请日：2018-11-19

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Chung-Hua Tsai ,  Tung-Hsing Wu ,  Lien-Fei Chen ,  Yu-Kun Lin ,  Yi-Hsin Huang ,  Han-Liang Chou

IPC: H04N19/85 ,  H04N19/70 ,  H04N19/184

CPC classification number: H04N19/85 ,  H04N19/184 ,  H04N19/70

Abstract: A video compression system includes a video encoder and a bitstream processing circuit. The video encoder is hardware that performs hardware video encoding upon frames to generate a first bitstream. The first bitstream is output from an entropy encoding circuit of the video encoder. The bitstream processing circuit performs a bitstream post-processing operation upon the first bitstream to produce a second bitstream that is different from the first bitstream, and outputs the second bitstream as a compression output of the frames.

公开(公告)号：US20180027244A1

公开(公告)日：2018-01-25

申请号：US15654706

申请日：2017-07-20

Applicant: MEDIATEK INC.

Inventor： Lien-Fei Chen ,  Tung-Hsing Wu ,  Li-Heng Chen ,  Han-Liang Chou

IPC: H04N19/172 ,  H04N19/149 ,  H04N19/174 ,  H04N19/124 ,  H04N19/159

CPC classification number: H04N19/172 ,  H04N19/124 ,  H04N19/149 ,  H04N19/152 ,  H04N19/159 ,  H04N19/164 ,  H04N19/174

Abstract: An exemplary video encoding apparatus has a video encoder, a transmitter, and a control circuit. The video encoder encodes a video sequence into a compressed video bitstream. The transmitter transmits the compressed video bitstream via a communication link. The control circuit adaptively adjusts an encoding behavior of the video encoder according to at least a transmission status of the communication link.