公开(公告)号：US10904577B2

公开(公告)日：2021-01-26

申请号：US16194396

申请日：2018-11-19

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Chung-Hua Tsai ,  Tung-Hsing Wu ,  Lien-Fei Chen ,  Yu-Kun Lin ,  Yi-Hsin Huang ,  Han-Liang Chou

IPC: H04N19/184 ,  H04N19/85 ,  H04N19/70

Abstract: A video compression system includes a video encoder and a bitstream processing circuit. The video encoder is hardware that performs hardware video encoding upon frames to generate a first bitstream. The first bitstream is output from an entropy encoding circuit of the video encoder. The bitstream processing circuit performs a bitstream post-processing operation upon the first bitstream to produce a second bitstream that is different from the first bitstream, and outputs the second bitstream as a compression output of the frames.

公开(公告)号：US20190246144A1

公开(公告)日：2019-08-08

申请号：US16194396

申请日：2018-11-19

Applicant: MEDIATEK INC.

Inventor： Li-Heng Chen ,  Chung-Hua Tsai ,  Tung-Hsing Wu ,  Lien-Fei Chen ,  Yu-Kun Lin ,  Yi-Hsin Huang ,  Han-Liang Chou

IPC: H04N19/85 ,  H04N19/70 ,  H04N19/184

CPC classification number: H04N19/85 ,  H04N19/184 ,  H04N19/70

Abstract: A video compression system includes a video encoder and a bitstream processing circuit. The video encoder is hardware that performs hardware video encoding upon frames to generate a first bitstream. The first bitstream is output from an entropy encoding circuit of the video encoder. The bitstream processing circuit performs a bitstream post-processing operation upon the first bitstream to produce a second bitstream that is different from the first bitstream, and outputs the second bitstream as a compression output of the frames.