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公开(公告)号：US11836315B2
公开(公告)日：2023-12-05
申请号：US17500108
申请日：2021-10-13
Inventor： Chulwoo Kim , Soonsung Ahn
IPC: G06F3/041 , G06F3/046 , G06F3/044 , G06F3/0354
CPC classification number: G06F3/04162 , G06F3/03545 , G06F3/046 , G06F3/0414 , G06F3/0441 , G06F3/0442 , G06F3/04166
Abstract: Disclosed is electronic device for identifying touch position, touch system including electronic device, and operation method thereof.
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公开(公告)号：US10897382B2
公开(公告)日：2021-01-19
申请号：US16454307
申请日：2019-06-27
Inventor： Chulwoo Kim , Hyunsu Park , Jin Cheol Sim
IPC: H04L25/49
Abstract: According to an embodiment of the inventive concept, a device for PAM-3 signaling includes an encoder selecting one of first to ninth transitions in first and second unit intervals that are successive and mapping data of three bits by using a remaining eight transitions other than the one selected among the first to ninth transitions, and an output driver receiving an output signal of the encoder via an input and generating a multi-level signal having an output voltage of first to third levels. The data of three bits is transmitted to a receiver terminal through the multi-level signal having the output voltage of the first to third levels during the first and second unit intervals that are successive. The device for PAM-3 signaling according to an embodiment of the inventive concept may transmit three bits during two unit intervals and may allow a receiver terminal to detect a windowing phenomenon.
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公开(公告)号：US11842022B2
公开(公告)日：2023-12-12
申请号：US17168387
申请日：2021-02-05
Inventor： Chulwoo Kim , Soonsung Ahn
IPC: G06F3/044 , G06F3/041 , G06F3/0354 , G06F3/046
CPC classification number: G06F3/0447 , G06F3/03545 , G06F3/046 , G06F3/0412 , G06F3/0445 , G06F3/0446 , G06F3/04162 , G06F3/04166 , G06F2203/04106
Abstract: Disclosed is an electronic device, which includes a plurality of driving coils that are sequentially arranged in a first direction in a plan view, a plurality of sensing electrodes that are spaced and insulated from the plurality of driving coils and are sequentially arranged in a second direction orthogonal or pseudo-orthogonal to the first direction in a plan view, and a processor that is electrically connected with the plurality of driving coils and the plurality of sensing electrodes. At least one of the plurality of sensing electrodes is electrically coupled with a stylus excited by a magnetic field generated by the plurality of driving coils. The processor applies a driving signal to the plurality of driving coils, receives a response signal to the driving signal from the plurality of sensing electrodes, and identifies a contact location of the stylus based on the response signal.
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公开(公告)号：US10491237B1
公开(公告)日：2019-11-26
申请号：US16242508
申请日：2019-01-08
Inventor： Chulwoo Kim , Chaekang Lim
Abstract: A continuous-time delta-sigma modulator includes a loop filter, a quantizer, a finite impulse response (FIR) filter, and a digital to analog converter. The loop filter integrates a difference between an input signal and a feedback signal. The quantizer quantizes a signal output from the loop filter to convert the quantized signal into a digital signal. The FIR filter performs an FIR filtering process on the digital signal output from the quantizer. The digital to analog converter converts a signal output from the FIR filter into an analog signal and outputs the converted analog signal as a feedback signal.
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公开(公告)号：US09191184B2
公开(公告)日：2015-11-17
申请号：US14281767
申请日：2014-05-19
Inventor： Young-Hyun Baek , Jun-Young Song , Chulwoo Kim , Hyun-Woo Lee
CPC classification number: H04L7/0037 , H04L7/0008 , H04L7/033
Abstract: A system includes a transmitter including: an aligner configured to align the phases of an input clock signal and data signal; and a transmission circuit configured to generate a transmission signal of which the phase and amplitude are controlled according to the aligned clock signal and the aligned data signal. The system may also include a receiver including: a clock extraction circuit configured to extract a temporary clock signal from the transmission signal; a data extraction circuit configured to extract a temporary data signal from the transmission signal; a clock delay selector configured to generate the clock signal by delaying the temporary clock signal according to a value of the temporary data signal; and a data recovery circuit configured to sample the temporary data signal according to the clock signal outputted from the clock delay selector and output a data signal.
Abstract translation: 一种系统包括：发射机，包括：对准器，被配置为对准输入时钟信号和数据信号的相位; 以及发送电路，被配置为根据对准的时钟信号和对准的数据信号生成相位和幅度被控制的发送信号。 该系统还可以包括：接收机，包括：时钟提取电路，被配置为从传输信号中提取临时时钟信号; 数据提取电路，被配置为从所述发送信号中提取临时数据信号; 时钟延迟选择器，被配置为通过根据临时数据信号的值延迟临时时钟信号来产生时钟信号; 以及数据恢复电路，被配置为根据从时钟延迟选择器输出的时钟信号对临时数据信号进行采样，并输出数据信号。
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Patent Agency Ranking
公开(公告)号：US20150036730A1
公开(公告)日：2015-02-05
申请号：US14446917
申请日：2014-07-30
Inventor： Chulwoo Kim , Yeonho Lee , Junyoung Song
CPC classification number: H04B17/10 , H04L7/033 , H04L25/0272
Abstract: An apparatus and a system for automatically tracking data speed are disclosed. An embodiment of the invention provides a transmitting apparatus for automatically tracking data speed that includes: an encoder configured to convert parallelized input data according to a preset signal rule into a first signal and a second signal, where the input data is inputted as a unit of n bits, the encoder outputs the first signal and the second signal such that, if the input data includes identical bit values consecutively, one of the first signal and the second signal is converted to include transition information instead of following a differential rule with respect to the other signal; a serializer configured to serialize the first signal and the second signal; and a transmitting part configured to transmit the serialized first signal and second signal.
Abstract translation: 公开了一种用于自动跟踪数据速度的装置和系统。 本发明的实施例提供了一种用于自动跟踪数据速度的发送装置，包括：编码器，被配置为将根据预设信号规则的并行输入数据转换为第一信号和第二信号，其中输入数据作为 n位，编码器输出第一信号和第二信号，使得如果输入数据连续包括相同的位值，则将第一信号和第二信号中的一个转换为包括转换信息，而不是遵循相对于 另一个信号; 串行器，被配置为串行化第一信号和第二信号; 以及发送部，被配置为发送所述串行化的第一信号和所述第二信号。
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公开(公告)号：US11088878B2
公开(公告)日：2021-08-10
申请号：US16932217
申请日：2020-07-17
Inventor： Chulwoo Kim , Jonghyuck Choi
Abstract: A transceiver includes a transmitter modulating a data signal into code information in a modulation section unit and individually supplying a common mode current to a plurality of transmission lines and a receiver detecting the code information according to a voltage level of each of the transmission lines and outputting the data signal.
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公开(公告)号：US09264155B2
公开(公告)日：2016-02-16
申请号：US14446917
申请日：2014-07-30
Inventor： Chulwoo Kim , Yeonho Lee , Junyoung Song
CPC classification number: H04B17/10 , H04L7/033 , H04L25/0272
Abstract: An apparatus and a system for automatically tracking data speed are disclosed. An embodiment of the invention provides a transmitting apparatus for automatically tracking data speed that includes: an encoder configured to convert parallelized input data according to a preset signal rule into a first signal and a second signal, where the input data is inputted as a unit of n bits, the encoder outputs the first signal and the second signal such that, if the input data includes identical bit values consecutively, one of the first signal and the second signal is converted to include transition information instead of following a differential rule with respect to the other signal; a serializer configured to serialize the first signal and the second signal; and a transmitting part configured to transmit the serialized first signal and second signal.
Abstract translation: 公开了一种用于自动跟踪数据速度的装置和系统。 本发明的实施例提供了一种用于自动跟踪数据速度的发送装置，包括：编码器，被配置为将根据预设信号规则的并行输入数据转换为第一信号和第二信号，其中输入数据作为 n位，编码器输出第一信号和第二信号，使得如果输入数据连续包括相同的位值，则将第一信号和第二信号中的一个转换为包括转换信息，而不是遵循相对于 另一个信号; 串行器，被配置为串行化第一信号和第二信号; 以及发送部，被配置为发送所述串行化的第一信号和所述第二信号。
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公开(公告)号：US12184290B2
公开(公告)日：2024-12-31
申请号：US18081027
申请日：2022-12-14
Inventor： Chulwoo Kim , Seung-Woo Park , Yoon-Jae Choi , Jin-Cheol Sim
IPC: H03L7/08 , H03K3/0233 , H03L7/097
Abstract: Disclosed in a PAM-4 receiver using pattern-based clock and data recovery circuitry, which includes an analog front end that receives an external signal and recovers channel loss to output a refined PAM-4 signal, a comparison unit that receives the PAM-4 signal and compares the PAM-4 signal with a reference voltage to generate a recovery signal, and a recovery unit that receives the recovery signal and recovers data and a clock. The analog front end includes an equalizer that matches amplitudes of all frequency components of the external signal and an amplifier that amplifies an output signal of the equalizer.
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公开(公告)号：US11979160B2
公开(公告)日：2024-05-07
申请号：US17961122
申请日：2022-10-06
Inventor： Chulwoo Kim , Jong-Hyuck Choi
IPC: H04B3/04 , H03K5/1252 , H03K17/687 , H04B10/69 , H04L27/01
CPC classification number: H03K5/1252 , H03K17/6872 , H04B10/6971 , H04L27/01
Abstract: A single-signal receiver including an active inductor continuous time linear equalizer and a reference voltage selection equalizer is provided. The single-signal receiver includes a continuous time linear equalizing unit to receive a single signal, and compensate for distortion of the single signal to generate an output, and a reference voltage selection equalizing unit to select one of a first reference voltage value and a second reference voltage value based on a previous output from a comparator, and sample the output from the continuous time linear equalizing unit, based on the one of the first reference voltage value and the second reference voltage value.
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