公开(公告)号：US20220357673A1

公开(公告)日：2022-11-10

申请号：US17488010

申请日：2021-09-28

Applicant: KLA Corporation

Inventor： Stilian Pandev ,  Min-Yeong Moon ,  Andrei V. Shchegrov ,  Jonathan Madsen ,  Dimitry Sanko ,  Liran Yerushalmi ,  Alexander Kuznetsov ,  Mahendra Dubey

IPC: G03F7/20

Abstract: A self-calibrating overlay metrology system may receive device overlay data from device targets on a sample, determine preliminary device overlay measurements for the device targets including device-scale features using an overlay recipe with the device overlay data as inputs, receive assist overlay data from sets of assist targets on the sample including device-scale features, where a particular set of assist targets includes one or more target pairs formed with two overlay targets having programmed overlay offsets of a selected value with opposite signs along a particular measurement direction. The system may further determine self-calibrating assist overlay measurements for the sets of assist targets based on the assist overlay data, where the self-calibrating assist overlay measurements are linearly proportional to overlay on the sample, and generate corrected overlay measurements for the device targets by adjusting the preliminary device overlay measurements based on the self-calibrating assist overlay measurements.

公开(公告)号：US20220020625A1

公开(公告)日：2022-01-20

申请号：US16931078

申请日：2020-07-16

Applicant: KLA Corporation

Inventor： Roie Volkovich ,  Liran Yerushalmi ,  Raviv Yohanan ,  Mark Ghinovker

IPC: H01L21/68 ,  G01B11/27

Abstract: A metrology system and metrology methods are disclosed. The metrology system comprises a set of device features on a first layer of a sample, a first set of target features on a second layer of the sample and overlapping the set of device features, and a second set of target features on the second layer of the sample and overlapping the set of device features. Relative positions of a first set of Moiré fringes and a second set of Moiré fringes indicate overlay error between the first layer of the sample and the second layer of the sample.

公开(公告)号：US11644419B2

公开(公告)日：2023-05-09

申请号：US17160547

申请日：2021-01-28

Applicant: KLA Corporation

Inventor： Roie Volkovich ,  Liran Yerushalmi ,  Amnon Manassen ,  Yoram Uziel

IPC: G01N21/41 ,  G01N21/3563 ,  G01N21/956 ,  G01B9/02 ,  G01N21/45 ,  G01N21/25

CPC classification number: G01N21/4133 ,  G01B9/02 ,  G01N21/25 ,  G01N21/3563 ,  G01N21/45 ,  G01N21/956 ,  G01N2021/3568

Abstract: A method for optical inspection includes illuminating a patterned polymer layer on a semiconductor wafer with optical radiation over a range of infrared wavelengths, measuring spectral properties of the optical radiation reflected from multiple points on the patterned polymer layer over the range of infrared wavelengths, and based on the measured spectral properties, computing a complex refractive index of the patterned polymer layer.

公开(公告)号：US20230128610A1

公开(公告)日：2023-04-27

申请号：US17510307

申请日：2021-10-25

Applicant: KLA CORPORATION

Inventor： Liran Yerushalmi ,  Alexander Kuznetsov

IPC: H01L21/67 ,  G06N3/08 ,  G06N3/04 ,  G06F17/18

Abstract: Two machine learning modules or models are used to generate a recipe. A first machine learning module determines a set of recipes based on measured signals. The second machine learning module analyzes the set of recipes based on a cost function to determine a final recipe. The second machine learning module also can determine settings if the set of recipes fail evaluation using the cost function.

公开(公告)号：US20220412734A1

公开(公告)日：2022-12-29

申请号：US17473742

申请日：2021-09-13

Applicant: KLA Corporation

Inventor： Stilian Pandev ,  Min-Yeong Moon ,  Andrei V. Shchegrov ,  Jonathan Madsen ,  Dimitry Sanko ,  Liran Yerushalmi ,  Alexander Kuznetsov ,  Mahendra Dubey

IPC: G01B21/24

Abstract: An overlay metrology system may receive overlay data for in-die overlay targets within various fields on a skew training sample from one or more overlay metrology tools, wherein the in-die overlay targets within the fields have a range programmed overlay offsets, wherein the fields are fabricated with a range of programmed skew offsets. The system may further generate asymmetric target signals for the in-die overlay targets using an asymmetric function providing a value of zero when physical overlay is zero and a sign indicative of a direction of physical overlay. The system may further generate corrected overlay offsets for the in-die overlay targets on the asymmetric target signals, generate self-calibrated overlay offsets for the in-die overlay targets based on the programmed overlay offsets and the corrected overlay offsets, generate a trained overlay recipe, and generate overlay measurements for in-die overlay targets on additional samples using the trained overlay recipe.

公开(公告)号：US11532566B2

公开(公告)日：2022-12-20

申请号：US16964714

申请日：2020-06-25

Applicant: KLA CORPORATION

Inventor： Roie Volkovich ,  Liran Yerushalmi ,  Raviv Yohanan ,  Mark Ghinovker

IPC: H01L23/544 ,  G01B21/22 ,  G03F7/20

Abstract: A target and method for using the same in the measurement of misregistration between at least a first layer and a second layer formed on a wafer in the manufacture of functional semiconductor devices on the wafer, the functional semiconductor devices including functional device structures (FDSTs), the target including a plurality of measurement structures (MSTs), the plurality of MSTs being part of the first layer and the second layer and a plurality of device-like structures (DLSTs), the plurality of DLSTs being part of at least one of the first layer and the second layer, the DLSTs sharing at least one characteristic with the FDSTs and the MSTs not sharing the at least one characteristic with the FDSTs.

公开(公告)号：US20220013468A1

公开(公告)日：2022-01-13

申请号：US16964714

申请日：2020-06-25

Applicant: KLA CORPORATION

Inventor： Roie Volkovich ,  Liran Yerushalmi ,  Raviv Yohanan ,  Mark Ghinovker

IPC: H01L23/544 ,  G01B21/22

Abstract: A target and method for using the same in the measurement of misregistration between at least a first layer and a second layer formed on a wafer in the manufacture of functional semiconductor devices on the wafer, the functional semiconductor devices including functional device structures (FDSTs), the target including a plurality of measurement structures (MSTs), the plurality of MSTs being part of the first layer and the second layer and a plurality of device-like structures (DLSTs), the plurality of DLSTs being part of at least one of the first layer and the second layer, the DLSTs sharing at least one characteristic with the FDSTs and the MSTs not sharing the at least one characteristic with the FDSTs.

公开(公告)号：US11880142B2

公开(公告)日：2024-01-23

申请号：US18118420

申请日：2023-03-07

Applicant: KLA Corporation

Inventor： Stilian Pandev ,  Min-Yeong Moon ,  Andrei V. Shchegrov ,  Jonathan Madsen ,  Dimitry Sanko ,  Liran Yerushalmi ,  Alexander Kuznetsov ,  Mahendra Dubey

IPC: G03F7/00

CPC classification number: G03F7/70633 ,  G03F7/70516 ,  G03F7/70775

Abstract: A self-calibrating overlay metrology system may receive device overlay data for a device targets on a sample from an overlay metrology tool, determine preliminary device overlay measurements for the device targets including device-scale features using an overlay recipe with the device overlay data as inputs, receive assist overlay data for one or more assist targets on the sample including device-scale features from the overlay metrology tool, where at least one of the one or more assist targets has a programmed overlay offset of a selected value along a particular measurement direction, determine self-calibrating assist overlay measurements for the one or more assist targets based on the assist overlay data, where the self-calibrating assist overlay measurements are linearly proportional to overlay on the sample, and generate corrected overlay measurements for the device targets by adjusting the preliminary device overlay measurements based on the self-calibrating assist overlay measurements.

公开(公告)号：US20230221656A1

公开(公告)日：2023-07-13

申请号：US18118420

申请日：2023-03-07

Applicant: KLA Corporation

Inventor： Stilian Pandev ,  Min-Yeong Moon ,  Andrei V. Shchegrov ,  Jonathan Madsen ,  Dimitry Sanko ,  Liran Yerushalmi ,  Alexander Kuznetsov ,  Mahendra Dubey

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/70516 ,  G03F7/70775

Abstract: A self-calibrating overlay metrology system may receive device overlay data for a device targets on a sample from an overlay metrology tool, determine preliminary device overlay measurements for the device targets including device-scale features using an overlay recipe with the device overlay data as inputs, receive assist overlay data for one or more assist targets on the sample including device-scale features from the overlay metrology tool, where at least one of the one or more assist targets has a programmed overlay offset of a selected value along a particular measurement direction, determine self-calibrating assist overlay measurements for the one or more assist targets based on the assist overlay data, where the self-calibrating assist overlay measurements are linearly proportional to overlay on the sample, and generate corrected overlay measurements for the device targets by adjusting the preliminary device overlay measurements based on the self-calibrating assist overlay measurements.

公开(公告)号：US11635682B2

公开(公告)日：2023-04-25

申请号：US16766807

申请日：2020-04-23

Applicant: KLA Corporation

Inventor： Roie Volkovich ,  Liran Yerushalmi ,  Achiam Bar

IPC: G03F7/20 ,  G03F1/70 ,  G01B11/24

Abstract: A method for process control in the manufacture of semiconductor devices including performing metrology on at least one Design of Experiment (DOE) semiconductor wafer included in a lot of semiconductor wafers, the lot forming part of a batch of semiconductor wafer lots, generating, based on the metrology, one or more correctables to a process used to manufacture the lot of semiconductor wafers and adjusting, based on the correctables, the process performed on at least one of; other semiconductor wafers included in the lot of semi-conductor wafers, and other lots of semiconductor wafers included in the batch.