公开(公告)号：US20250005209A1

公开(公告)日：2025-01-02

申请号：US18343609

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Debayan Das ,  Santosh Ghosh ,  Manoj Sastry

IPC: G06F21/75

Abstract: Techniques for attenuation and obfuscation to mitigate power and/or electromagnetic (EM) field attacks on encryption circuitry are described. In certain examples, a system includes a processor core; and an accelerator coupled to the processor core, the accelerator comprising: encryption circuitry, coupled to a power source, to encrypt data into encrypted data, time-domain obfuscation control circuitry to connect and disconnect one or more capacitors to the encryption circuitry during the encrypt to provide obfuscation across a time-domain to maintain a software observable power consumption of the accelerator to about a value, and signature attenuation control circuitry to selectively connect the encryption circuitry during the encrypt to a shunt to drain power to maintain the software observable power consumption of the accelerator at about the value.

公开(公告)号：US20250005205A1

公开(公告)日：2025-01-02

申请号：US18216436

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Iwan Grau ,  Anas Hlayhel ,  Santosh Ghosh ,  Sonal Waydande ,  Matthew Wise ,  William Penner ,  Enrico Carrieri

IPC: G06F21/72 ,  G06F21/74

Abstract: An example of an apparatus may include first circuitry that is to be selectively locked and unlocked, second circuitry to process one or more tokens including an unlock token for the first circuitry, and hardware authentication circuitry to authenticate the unlock token for the first circuitry in response to a request from the second circuitry. The apparatus may further include hardware ungate circuitry to selectively gate and ungate one or more features of the first circuitry in response to an indication that the first circuitry is one of locked or unlocked. Other examples are disclosed and claimed.

公开(公告)号：US12137169B2

公开(公告)日：2024-11-05

申请号：US17854911

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/00 ,  H04L9/06 ,  H04L9/08 ,  H04L9/30

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

公开(公告)号：US20240220640A1

公开(公告)日：2024-07-04

申请号：US18148638

申请日：2022-12-30

Applicant: Intel Corporation

Inventor： Daniël Kuijsters ,  Christoph Dobraunig ,  Santosh Ghosh

IPC: G06F21/60 ,  G06F21/54 ,  G06F21/55

CPC classification number: G06F21/602 ,  G06F21/54 ,  G06F21/554

Abstract: In one example an apparatus comprises a first input node to receive a first input bit, an encryption circuit to split the first input bit into a first share and a second share, and perform an encryption function on the first input share and the second input share to generate a first output share and a second output share, an error tag generator circuit to calculate a first error tag from the first input share and the second input share, and calculate a second error tag from the first output share and the second output share, an error detection circuit to generate an error signal when the first error tag does not match the second error tag.

公开(公告)号：US11985226B2

公开(公告)日：2024-05-14

申请号：US17133183

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Marcio Juliato ,  Manoj Sastry

IPC: H04L9/06 ,  H03M13/15 ,  H04L9/00

CPC classification number: H04L9/0643 ,  H03M13/151 ,  H04L9/002

Abstract: An apparatus comprises an input register comprising a state register and a parity field, a first round secure hash algorithm (SHA) datapath communicatively coupled to the state register, comprising a first section to perform a θ step of a SHA calculation, a second section to perform a ρ step and a ρ step of the SHA calculation, a third section to perform a χ step of the SHA calculation and a fourth section to perform a τ step of the SHA calculation.

公开(公告)号：US11954045B2

公开(公告)日：2024-04-09

申请号：US17485213

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael LeMay ,  Santosh Ghosh ,  Sergej Deutsch

IPC: G06F12/14 ,  G06F12/0802 ,  G06F21/55 ,  G06F21/56 ,  G06F21/79

CPC classification number: G06F12/1408 ,  G06F12/0802 ,  G06F21/554 ,  G06F2212/466

Abstract: Technologies disclosed herein provide one example of a system that includes processor circuitry and integrity circuitry. The processor circuitry is to receive a first request associated with an application to perform a memory access operation for an address range in a memory allocation of memory circuitry. The integrity circuitry is to determine a location of a metadata region within a cacheline that includes at least some of the address range, identify a first portion of the cacheline based at least in part on a first data bounds value stored in the metadata region, generate a first integrity value based on the first portion of the cacheline, and prevent the memory access operation in response to determining that the first integrity value does not correspond to a second integrity value stored in the metadata region.

公开(公告)号：US11909857B2

公开(公告)日：2024-02-20

申请号：US16724732

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Marcio Juliato ,  Rafael Misoczki ,  Manoj Sastry ,  Liuyang Yang ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Xiruo Liu

IPC: H04L9/06 ,  H04L9/32 ,  H04W4/40

CPC classification number: H04L9/0631 ,  H04L9/0637 ,  H04L9/3242 ,  H04W4/40 ,  H04L2209/26 ,  H04L2209/601

Abstract: Systems, apparatus, methods, and techniques for functional safe execution of encryption operations are provided. A fault tolerant counter and a complementary pair of encryption flows are provided. The fault tolerant counter may be based on a gray code counter and a hamming distance checker. The complementary pair of encryption flows have different implementations. The output from the complementary pair of encryption flows can be compared, and where different, errors generated.

公开(公告)号：US11792005B2

公开(公告)日：2023-10-17

申请号：US17699830

申请日：2022-03-21

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Andrew H. Reinders ,  Manoj Sastry

IPC: H04L9/40 ,  H04L9/30

CPC classification number: H04L9/3093 ,  H04L2209/12

Abstract: A method comprises fetching, by fetch circuitry, an encoded butterfly instruction comprising an opcode, a first source identifier, a second source identifier, a third source identifier, and two destination identifiers, decoding, by decode circuitry, the decoded butterfly instruction to generate a decoded butterfly instruction, and executing, by execution circuitry, the decoded butterfly instruction to retrieve operands representing a first input polynomial-coefficient from the first source, a second input polynomial-coefficient from the second source, and a primitive nth root of unity from the third source, perform, in an atomic fashion, a butterfly operation to generate a first output polynomial-coefficient and a second output polynomial-coefficient, and store the first output coefficient and the second output coefficient in a register file accessible to the execution circuitry.

公开(公告)号：US20230091951A1

公开(公告)日：2023-03-23

申请号：US17478579

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Manoj Sastry

IPC: H04L9/30 ,  H04L9/08 ,  G06F7/53 ,  G06F7/487

Abstract: Polynomial multiplication for side-channel protection in cryptography is described. An example of a apparatus includes one or more processors to process data; a memory to store data; and polynomial multiplier circuitry to multiply a first polynomial by a second polynomial, the first polynomial and the second polynomial each including a plurality of coefficients, the polynomial multiplier circuitry including a set of multiplier circuitry, wherein the polynomial multiplier circuitry is to select a first coefficient of the first polynomial for processing, and multiply the first coefficient of the first polynomial by all of the plurality of coefficients of the second polynomial in parallel using the set of multiplier circuits.

公开(公告)号：US11575504B2

公开(公告)日：2023-02-07

申请号：US16776467

申请日：2020-01-29

Applicant: Intel Corporation

Inventor： David M. Durham ,  Michael LeMay ,  Michael E. Kounavis ,  Santosh Ghosh ,  Sergej Deutsch ,  Anant Vithal Nori ,  Jayesh Gaur ,  Sreenivas Subramoney ,  Karanvir S. Grewal

IPC: H04L9/06 ,  G06F9/30 ,  G06F12/1027

Abstract: A processor comprises a first register to store an encoded pointer to a memory location. First context information is stored in first bits of the encoded pointer and a slice of a linear address of the memory location is stored in second bits of the encoded pointer. The processor also includes circuitry to execute a memory access instruction to obtain a physical address of the memory location, access encrypted data at the memory location, derive a first tweak based at least in part on the encoded pointer, and generate a keystream based on the first tweak and a key. The circuitry is to further execute the memory access instruction to store state information associated with memory access instruction in a first buffer, and to decrypt the encrypted data based on the keystream. The keystream is to be generated at least partly in parallel with accessing the encrypted data.