COMBINED PROTECTION OF SYMMETRIC-KEY PRIMITIVES AGAINST SIDE-CHANNEL AND FAULT ATTACKS
Abstract:
In one example an apparatus comprises a first input node to receive a first input bit, an encryption circuit to split the first input bit into a first share and a second share, and perform an encryption function on the first input share and the second input share to generate a first output share and a second output share, an error tag generator circuit to calculate a first error tag from the first input share and the second input share, and calculate a second error tag from the first output share and the second output share, an error detection circuit to generate an error signal when the first error tag does not match the second error tag.
Information query
Patent Agency Ranking
0/0