公开(公告)号：US10108512B2

公开(公告)日：2018-10-23

申请号：US15089316

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/22 ,  G06F11/00 ,  G06F11/10 ,  G11C29/52

Abstract: Embodiments are generally directed to validation of memory on-die error correction code. An embodiment of a memory device includes one or more memory arrays for the storage of data; control logic to control operation of the memory device; and ECC (error correction code) logic, including ECC correction logic to correct data and ECC generation logic to generate ECC code bits and store the ECC bits in the one or more memory arrays. In a validation mode to validate operation of the ECC logic, the control logic is to allow generation of ECC code bits for a first test value and disable generation of ECC code bits for a second test value.

公开(公告)号：US10083737B2

公开(公告)日：2018-09-25

申请号：US15633604

申请日：2017-06-26

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  John B. Halbert

IPC: G11C11/4078 ,  G06F13/16 ,  G11C11/406 ,  G11C11/408 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C11/4078 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

公开(公告)号：US10067820B2

公开(公告)日：2018-09-04

申请号：US15650479

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  George Vergis

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/44 ,  G11C7/10 ,  G11C5/04 ,  G11C29/04

Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

公开(公告)号：US10031684B2

公开(公告)日：2018-07-24

申请号：US15788679

申请日：2017-10-19

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Kuljit S. Bains

IPC: G11C7/00 ,  G06F3/06 ,  G11C7/10

Abstract: Examples include techniques for a write zero operation. Example techniques include forwarding a write 0 command to a memory device to cause internal activations of column select lines of one or more blocks of memory to cause bit values or contents of the one or more blocks to have or store a value of 0.

公开(公告)号：US09871519B2

公开(公告)日：2018-01-16

申请号：US15359573

申请日：2016-11-22

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Nadav Bonen ,  Christopher E. Cox ,  Alexey Kostinsky

IPC: H03K19/00 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/0185 ,  G06F13/40 ,  G06F3/06

CPC classification number: H03K19/0005 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/4086 ,  H03K19/0008 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.

公开(公告)号：US09858980B2

公开(公告)日：2018-01-02

申请号：US15213235

申请日：2016-07-18

Applicant: INTEL CORPORATION

Inventor： Kuljit S. Bains

IPC: G11C11/40 ,  G11C11/406 ,  G06F12/02

CPC classification number: G11C11/40615 ,  G06F12/023 ,  G06F2212/1016 ,  G11C11/40611 ,  G11C11/40618 ,  G11C2211/4061

Abstract: On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch from a currently-applied refresh rate to a different refresh rate. In response to the condition, the refresh rate is dynamically switched. The switching does not require a change of a mode register. Thus, a refresh rate for the memory device can be dynamically changed on the fly.

公开(公告)号：US09761298B2

公开(公告)日：2017-09-12

申请号：US15364123

申请日：2016-11-29

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G11C11/406 ,  G06F3/06 ,  G06F12/06

CPC classification number: G11C11/40618 ,  G06F3/0616 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0646 ,  G06F12/0684 ,  G11C7/1072 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076

Abstract: Techniques and mechanisms to facilitate an operational mode of a memory device to prepare for a targeted refresh of a row in memory. In an embodiment, the memory device performs one or more operations while in the mode to prepare for a future command from a memory controller, the command to implement, at least in part, a targeted refresh of a row in a first bank of the memory device. Prior to such a command, the memory device services another command from the memory controller. In another embodiment, servicing the other command includes the memory device accessing a second bank of the memory device while the memory device operates in the mode, and before completion of an expected future targeted row refresh.

公开(公告)号：US20170255406A1

公开(公告)日：2017-09-07

申请号：US15277182

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Kuljit S. Bains

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/068 ,  G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C16/20

Abstract: Examples include techniques for a write zero operation. Example techniques include forwarding a write 0 command to a memory device to cause internal activations of column select lines of one or more blocks of memory to cause bit values or contents of the one or more blocks to have or store a value of 0.

公开(公告)号：US20170255387A1

公开(公告)日：2017-09-07

申请号：US15277159

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Christopher E. Cox ,  Kuljit S. Bains ,  James A. McCall

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/16 ,  G11C7/10 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2263 ,  G11C2207/229

Abstract: Examples include techniques to cause a content pattern to be stored to memory cells of a memory device. Example techniques include forwarding a content pattern to a memory device for storage to registers maintained at the memory device. A command is generated and forwarded to the memory device to cause the content pattern to be stored to at least a portion of memory cells for the memory device responsive to a write request to the memory device having a matching content pattern.

公开(公告)号：US20170060681A1

公开(公告)日：2017-03-02

申请号：US14998184

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： John B. Halbert ,  Kuljit S. Bains

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1048 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1068 ,  G11C11/401 ,  G11C29/42 ,  G11C29/52 ,  H03M13/095 ,  H03M13/6566

Abstract: An error check and scrub (ECS) mode enables a memory device to perform error checking and correction (ECC) and count errors. An associated memory controller triggers the ECS mode with a trigger sent to the memory device. The memory device includes multiple addressable memory locations, which can be organized in segments such as wordlines. The memory locations store data and have associated ECC information. In the ECS mode, the memory device reads one or more memory locations and performs ECC for the one or more memory locations based on the ECC information. The memory device counts error information including a segment count indicating a number of segments having at least a threshold number of errors, and a maximum count indicating a maximum number of errors in any segment.

Abstract translation: 错误检查和擦除（ECS）模式使存储器件能够执行错误检查和校正（ECC）并计数错误。 相关联的存储器控​​制器通过触发发送到存储器件的触发器来触发ECS模式。 存储器件包括多个可寻址的存储器位置，其可以被组织成诸如字线的段。 存储器位置存储数据并具有相关联的ECC信息。 在ECS模式中，存储器件读取一个或多个存储器位置，并且基于ECC信息为一个或多个存储器位置执行ECC。 存储器装置对包括指示具有至少阈值数量的错误的段的数量的段计数以及指示任何段中的最大错误数的最大计数的错误信息进行计数。