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1.发明授权公开(公告)号：US10545735B2
公开(公告)日：2020-01-28
申请号：US15813021
申请日：2017-11-14
Applicant: Intel Corporation
Inventor： Polychronis Xekalakis , Jason M. Agron
Abstract: An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. For example, one embodiment of a processor comprises: a dual return stack buffer (DRSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB.
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2.发明申请公开(公告)号：US20190163642A1
公开(公告)日：2019-05-30
申请号：US15823387
申请日：2017-11-27
Applicant: Intel Corporation
Inventor： Girish Venkatasubramanian , Jason M. Agron , Cristiano Pereira , Rangeen Basu Roy Chowdhury
IPC: G06F12/1027 , G06F12/1009 , G06F12/12 , G06F9/38 , G06F9/32 , G06F12/0831
Abstract: A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.
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公开(公告)号：US20160283234A1
公开(公告)日：2016-09-29
申请号：US14672158
申请日：2015-03-28
Applicant: Intel Corporation
Inventor： POLYCHRONIS XEKALAKIS , Jamison D. Collins , Jason M. Agron
IPC: G06F9/30
CPC classification number: G06F9/455 , G06F9/45516
Abstract: Methods and apparatuses relating to preventing the execution of a modified instruction. In one embodiment, an apparatus includes a hardware binary translator to translate an instruction to a translated instruction, and a consistency hardware manager to prevent execution of the translated instruction by a hardware processor on detection of a modification to a virtual to physical address mapping of the instruction after the translation.
Abstract translation: 与防止修改指令的执行有关的方法和装置。 在一个实施例中，一种装置包括用于将指令转换为转换的指令的硬件二进制转换器和一致性硬件管理器，以防止硬件处理器在检测到对虚拟对物理地址映射的修改时执行转换的指令 翻译后的指示。
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公开(公告)号：US10296343B2
公开(公告)日：2019-05-21
申请号：US15474666
申请日：2017-03-30
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Jason M. Agron , Youfeng Wu
Abstract: A processing device including a first shadow register, a second shadow register, and an instruction execution circuit, communicatively coupled to the first shadow register and the second shadow register, to receive a sequence of instructions comprising a first local commit marker, a first global commit marker, and a first register access instruction referencing an architectural register, speculatively execute the first register access instruction to generate a speculative register state value associated with a physical register, responsive to identifying the first local commit marker, store, in the first shadow register, the speculative register state value, and responsive to identifying the first global commit marker, store, in the second shadow register, the speculative register state value.
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公开(公告)号：US20180285112A1
公开(公告)日：2018-10-04
申请号：US15474666
申请日：2017-03-30
Applicant: Intel Corporation
Inventor： Vineeth Mekkat , Jason M. Agron , Youfeng Wu
IPC: G06F9/30 , G06F12/0875 , G06F9/38
CPC classification number: G06F9/30174 , G06F9/30101 , G06F9/3842 , G06F9/467 , G06F12/0875 , G06F2212/1016 , G06F2212/452 , G06F2212/507
Abstract: A processing device including a first shadow register, a second shadow register, and an instruction execution circuit, communicatively coupled to the first shadow register and the second shadow register, to receive a sequence of instructions comprising a first local commit marker, a first global commit marker, and a first register access instruction referencing an architectural register, speculatively execute the first register access instruction to generate a speculative register state value associated with a physical register, responsive to identifying the first local commit marker, store, in the first shadow register, the speculative register state value, and responsive to identifying the first global commit marker, store, in the second shadow register, the speculative register state value.
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Patent Agency Ranking
公开(公告)号：US09880842B2
公开(公告)日：2018-01-30
申请号：US13834049
申请日：2013-03-15
Applicant: Intel Corporation
Inventor： Jayaram Bobba , Ruchira Sasanka , Jeffrey J. Cook , Abhinav Das , Arvind Krishnaswamy , David J. Sager , Jason M. Agron
CPC classification number: G06F9/3005 , G06F8/433 , G06F11/0715 , G06F11/0721 , G06F11/076 , G06F11/3466
Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.
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公开(公告)号：US20170192788A1
公开(公告)日：2017-07-06
申请号：US14988298
申请日：2016-01-05
Applicant: Intel Corporation
Inventor： Oleg Margulis , Jason M. Agron , Tyler N. Sondag
IPC: G06F9/30
CPC classification number: G06F9/30185 , G06F9/30138 , G06F9/30174 , G06F9/4552
Abstract: A processing system implementing techniques for binary translation support using processor instruction prefixes is provided. In one embodiment, the processing system includes a register bank having a plurality of registers to store data for use in executing instructions and a processor core coupled to the register bank. An instruction to be executed by the processor core is received. The instruction is associated with a binary translator operation to translate input instruction sequences to output instruction sequences. An opcode prefix referencing an extended register of the plurality of registers to be used during the binary translator operation. The extended register preserves a source register value of the plurality of registers.
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公开(公告)号：US09990233B2
公开(公告)日：2018-06-05
申请号：US14129420
申请日：2013-06-28
Applicant: Intel Corporation
Inventor： Abhik Sarkar , Jiwei Lu , Palanivelrajan Rajan Shanmugavelayutham , Jason M. Agron , Koichi Yamada
CPC classification number: G06F9/5038 , G06F8/61 , G06F8/62 , G06F9/45516 , G06F9/485 , G06F9/5016 , G06F12/0253 , G06F12/0802 , G06F2212/1044 , G06F2212/60
Abstract: Technologies for partial binary translation on multi-core platforms include a shared translation cache, a binary translation thread scheduler, a global installation thread, and a local translation thread and analysis thread for each processor core. On detection of a hotspot, the thread scheduler first resumes the global thread if suspended, next activates the global thread if a translation cache operation is pending, and last schedules local translation or analysis threads for execution. Translation cache operations are centralized in the global thread and decoupled from analysis and translation. The thread scheduler may execute in a non-preemptive nucleus, and the translation and analysis threads may execute in a preemptive runtime. The global thread may be primarily preemptive with a small non-preemptive nucleus to commit updates to the shared translation cache. The global thread may migrate to any of the processor cores. Forward progress is guaranteed. Other embodiments are described and claimed.
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9.发明授权公开(公告)号：US09817642B2
公开(公告)日：2017-11-14
申请号：US14751052
申请日：2015-06-25
Applicant: Intel Corporation
Inventor： Polychronis Xekalakis , Jason M. Agron
CPC classification number: G06F8/41 , G06F8/52 , G06F9/30054 , G06F9/30145 , G06F9/30174 , G06F9/30185 , G06F9/3806 , G06F9/4484 , G06F9/455 , G06F9/4552
Abstract: An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. An embodiment of a processor includes: a dual return stack buffer (DRSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB.
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公开(公告)号：US20170286110A1
公开(公告)日：2017-10-05
申请号：US15087786
申请日：2016-03-31
Applicant: Intel Corporation
Inventor： Jason M. Agron , Alex Merrick , Vineeth Mekkat
CPC classification number: G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/3832 , G06F12/0875 , G06F2212/452
Abstract: A hardware-software co-designed processor includes a front end to decode an instruction, an execution unit to execute the instruction, an auxiliary cache to store auxiliary information for consumption during execution of the instruction, an instruction blender, and a retirement unit to retire the instruction. The auxiliary information may include long immediate values, non-working instructions for emulating an untranslated instruction stream, or execution hints, and is not decoded by the front end. The auxiliary cache includes circuitry to receive the auxiliary information from a binary translator, to store the auxiliary information in the auxiliary cache, and to provide the auxiliary information to the instruction blender prior to execution. The instruction blender includes circuitry to receive the auxiliary information, to blend the instruction with the auxiliary information, and to provide the blended instruction to the execution unit. Use of the auxiliary cache may reduce fetch and decode bandwidth requirements.
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