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公开(公告)号：US20210410341A1
公开(公告)日：2021-12-30
申请号：US17471396
申请日：2021-09-10
Applicant: Intel Corporation
Inventor： Boon Ping Koh , Twan Sing Loo , Yew San Lim , Tin Poay Chuah
Abstract: Particular embodiments described herein provide for an electronic device that can be configured to include a support structure that includes a radiation shield groove that extends past a surface of the support structure and into the support structure, a radiation source on the substrate, and a radiation shield around the radiation source, where the radiation shield includes a wall secured to the support structure and a groove channel coupling wall that extends past a surface of the support structure and into the radiation shield groove.
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公开(公告)号：US10796999B2
公开(公告)日：2020-10-06
申请号：US16284218
申请日：2019-02-25
Applicant: Intel Corporation
Inventor： Boon Ping Koh , Eng Huat Goh , Jiun Hann Sir , Khang Choong Yong , Min Suet Lim , Wil Choon Song
IPC: H01L23/538 , H01L25/065 , H01L25/00 , H01L23/31 , H01L23/498 , H01L23/00
Abstract: A semiconductor apparatus includes a floating-bridge interconnect that couples two semiconductive devices that are arranged across a middle semiconductive device. The floating-bridge interconnect can be semiconductive material such as a silicon bridge, or it can be an organic bridge. Computing functions required in one of the two semiconductive devices can be off-loaded to any of the floating-bridge interconnect or the other of the two semiconductive devices.
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3.发明授权公开(公告)号：US10978434B2
公开(公告)日：2021-04-13
申请号：US16774904
申请日：2020-01-28
Applicant: Intel Corporation
Inventor： Bok Eng Cheah , Jackson Chung Peng Kong , Boon Ping Koh , Kooi Chi Ooi
IPC: H01L25/16 , H01L23/498 , H01L25/00 , H01Q21/22 , H01Q1/52 , H01Q21/00 , H01Q1/22 , H01L23/00 , H01L23/66 , H01L23/552 , H01L23/538
Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.
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公开(公告)号：US10939540B2
公开(公告)日：2021-03-02
申请号：US16399825
申请日：2019-04-30
Applicant: Intel Corporation
Inventor： Tin Poay Chuah , Yew San Lim , Boon Ping Koh , Phaik Kiau Tan
Abstract: A folded circuit board includes a first circuit board and a second circuit board. The first circuit board and second circuit board are coupled together through a flexible interconnect. One or more folding guides are coupled to one of the first circuit board or second circuit board. The one or more folding guides extend beyond a first edge of the one of the first circuit board or second circuit board. The one or more folding guides include a curved sidewall configured to guide the flexible interconnect when the first circuit board is folded over the second circuit board. In one embodiment, the one or more folding guides are grounded to reduce EMI emissions.
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公开(公告)号：US20160211619A1
公开(公告)日：2016-07-21
申请号：US14601403
申请日：2015-01-21
Applicant: Intel Corporation
Inventor： Jackson Chung Peng Kong , Bok Eng Cheah , Howard L Heck , Kuan-Yu Chen , Boon Ping Koh , Min Keen Tang , Kooi Chi Ooi
IPC: H01R13/648 , H01R24/66
CPC classification number: H01R13/6485 , H01R24/66 , H01R2107/00
Abstract: In one example an electronic device comprises a housing. A receptacle in the housing comprising an opening at a distal end to receive a plug and an electrostatic conductor assembly positioned proximate the opening in the receptacle, wherein the electrostatic conductor assembly is coupled to a dedicated electrical discharge path. Other examples may be described.
Abstract translation: 在一个示例中，电子设备包括壳体。 壳体中的容器包括在远端处的开口，用于容纳插头和靠近插座中的开口定位的静电导体组件，其中静电导体组件耦合到专用放电路径。 可以描述其他示例。
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Patent Agency Ranking
公开(公告)号：US11658127B2
公开(公告)日：2023-05-23
申请号：US16454423
申请日：2019-06-27
Applicant: Intel Corporation
Inventor： Eng Huat Goh , Jiun Hann Sir , Khang Choong Yong , Boon Ping Koh , Wil Choon Song , Min Suet Lim
IPC: H01L23/552 , H01L23/00 , H01L23/498
CPC classification number: H01L23/552 , H01L23/49805 , H01L23/49816 , H01L24/09
Abstract: Embodiments include semiconductor packages and method of forming the semiconductor packages. A semiconductor package includes a package substrate on a substrate, a die on the package substrate, and a conductive stiffener over the package substrate and the substrate. The conductive stiffener surrounds the package substrate, where the conductive stiffener has a top portion and a plurality of sidewalls, and where the top portion is directly disposed on the package substrate, and the sidewalls are vertically disposed on the substrate. The semiconductor package also includes the substrate that has a plurality of conductive pads, where the conductive pads are conductively coupled to a ground source. The conductive stiffener may conductively couple the package substrate to the conductive pads of the substrate. The top portion may have a cavity that surrounds the die, where the top portion is directly disposed on a plurality of outer edges of the package substrate.
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公开(公告)号：US11652057B2
公开(公告)日：2023-05-16
申请号：US16405610
申请日：2019-05-07
Applicant: Intel Corporation
Inventor： Khang Choong Yong , Eng Huat Goh , Min Suet Lim , Robert Sankman , Telesphor Kamgaing , Wil Choon Song , Boon Ping Koh
IPC: H01L23/538 , H01L23/31 , H01L23/48 , H01L25/065
CPC classification number: H01L23/5381 , H01L23/3178 , H01L23/3185 , H01L23/481 , H01L25/0655
Abstract: Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.
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公开(公告)号：US11211714B2
公开(公告)日：2021-12-28
申请号：US16462516
申请日：2017-11-21
Applicant: Intel Corporation
Inventor： Eng Huat Goh , Min Suet Lim , Boon Ping Koh , Wil Choon Song , Khang Choong Yong
Abstract: Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.
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9.发明申请公开(公告)号：US20200168592A1
公开(公告)日：2020-05-28
申请号：US16774904
申请日：2020-01-28
Applicant: Intel Corporation
Inventor： Bok Eng Cheah , Jackson Chung Peng Kong , Boon Ping Koh , Kooi Chi Ooi
IPC: H01L25/16 , H01L23/00 , H01Q1/22 , H01Q21/00 , H01Q1/52 , H01Q21/22 , H01L23/498 , H01L25/00 , H01L23/538 , H01L23/552 , H01L23/66
Abstract: A system-in-package includes a package substrate that at least partially surrounds an embedded radio-frequency integrated circuit chip and a processor chip mated to a redistribution layer. A wide-band phased-array antenna module is mated to the package substrate with direct interconnects from the radio-frequency integrated circuit chip to antenna patches within the antenna module. Additionally, fan-out antenna pads are also coupled to the radio-frequency integrated circuit chip.
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公开(公告)号：US20190261504A1
公开(公告)日：2019-08-22
申请号：US16399825
申请日：2019-04-30
Applicant: Intel Corporation
Inventor： Tin Poay Chuah , Yew San Lim , Boon Ping Koh , Phaik Kiau Tan
Abstract: A folded circuit board includes a first circuit board and a second circuit board. The first circuit board and second circuit board are coupled together through a flexible interconnect. One or more folding guides are coupled to one of the first circuit board or second circuit board. The one or more folding guides extend beyond a first edge of the one of the first circuit board or second circuit board. The one or more folding guides include a curved sidewall configured to guide the flexible interconnect when the first circuit board is folded over the second circuit board. In one embodiment, the one or more folding guides are grounded to reduce EMI emissions.
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