公开(公告)号：US10051584B2

公开(公告)日：2018-08-14

申请号：US15828455

申请日：2017-12-01

Applicant: Intel IP Corporation

Inventor： Shahar Gross ,  Ran Shimon ,  Roy Amel ,  Ofer Benjamin ,  Slava Vaysman

IPC: H04B1/04 ,  H04W52/52 ,  H04W52/08 ,  H04B17/13

CPC classification number: H04W52/52 ,  H03F3/189 ,  H03F3/24 ,  H03F2200/451 ,  H03G3/3042 ,  H03G3/3047 ,  H04B1/0475 ,  H04B17/13 ,  H04B2001/0416 ,  H04W52/08

Abstract: The present disclosure relates to a transmitter for transmitting a transmit signal comprising a first signal portion and a second signal portion. The transmitter comprises a power amplifier configured to amplify the transmit signal. The power amplifier is prone to undesired gain variations during the first and the second signal portion. The transmitter further comprises a transmit feedback receiver coupled to an output of the power amplifier and configured to feed back the transmit signal to generate a fed back first signal portion and a fed back second signal portion. Processing circuitry is configured to determine a first gain relation between the fed back first signal portion and the first signal portion and to determine at least one second gain relation between the fed back second signal portion and the second signal portion. Power adjustment circuitry is configured to adjust a transmit power of the transmit signal according to a variation between the first gain relation and the second gain relation.

公开(公告)号：US10952250B2

公开(公告)日：2021-03-16

申请号：US16474565

申请日：2017-02-07

Applicant: Intel IP Corporation

Inventor： Roy Amel ,  Shahar Gross ,  Ofer Benjamin

IPC: H04W74/08 ,  H04B1/16

Abstract: A receiver for detecting channel occupancy of a radio channel is provided. The receiver includes an oscillation circuit configured to generate an oscillation signal. The oscillation circuit is configured to alternate a frequency of the oscillation signal between at least two different frequency values. Further, the receiver includes a down-conversion circuit configured to generate, based on a received radio frequency signal and the oscillation signal, one of an in-phase component and a quadrature component of a baseband signal. The receiver additionally includes a processing circuit configured to calculate, based on the in-phase component or the quadrature component, a signal power of the radio frequency signal.

公开(公告)号：US10299290B2

公开(公告)日：2019-05-21

申请号：US15281111

申请日：2016-09-30

Applicant: INTEL IP CORPORATION

Inventor： Roy Amel ,  Noam Ginsburg ,  Ofer Benjamin ,  Shahar Gross

IPC: H04B1/00 ,  H04B15/00 ,  H04W74/00 ,  G01S7/02 ,  H04K3/00 ,  H04W88/06

Abstract: Some demonstrative embodiments include apparatuses, devices, systems and methods of radar detection. For example, an apparatus may include a first detector component to detect energy over a wireless communication channel; a second detector component to detect a signal over the wireless communication channel, and to determine at least a classification of the signal as a radar-type or a non-radar type; a storage component to store radar detection information corresponding to signals detected by the second detector component, the radar detection information including at least the classification of the signal and one or more characteristics of the signal; and a controller to activate the second detector component upon detection of the energy by the first detector component, the controller configured to cause a radar-detection analysis of the radar detection information corresponding to a predefined time period.

公开(公告)号：US20180191489A1

公开(公告)日：2018-07-05

申请号：US15395504

申请日：2016-12-30

Applicant: Intel IP Corporation

Inventor： Elan Banin ,  Roy Amel ,  Ran Shimon ,  Ashoke Ravi ,  Nati Dinur

IPC: H04L7/033 ,  H04L27/12 ,  H04L27/26

CPC classification number: H03L7/08 ,  H03L7/085 ,  H04L27/0014 ,  H04L2027/0053 ,  H04L2027/0067

Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.

公开(公告)号：US09813190B1

公开(公告)日：2017-11-07

申请号：US15200924

申请日：2016-07-01

Applicant: Intel IP Corporation

Inventor： Ilan Sutskover ,  Roy Nahum ,  Yuval Dafna ,  Ran Shimon ,  Tzahi Weisman ,  Roy Amel

IPC: H03H7/40 ,  H04L1/00 ,  H04L12/26 ,  H04L25/03 ,  H04L12/741 ,  H04L7/00 ,  H04L27/26

CPC classification number: H04L1/0042 ,  H03F1/3247 ,  H03F3/24 ,  H03F2201/3233 ,  H04L7/0008 ,  H04L25/03 ,  H04L25/03847 ,  H04L27/265 ,  H04L27/368 ,  H04L43/028 ,  H04L45/745

Abstract: Described herein are technologies related to an implementation of a closed-loop system to measure and compensate non-linearity in a transceiver circuitry of a device.

公开(公告)号：US10680619B2

公开(公告)日：2020-06-09

申请号：US16170716

申请日：2018-10-25

Applicant: Intel IP Corporation

Inventor： Elan Banin ,  Roy Amel ,  Ran Shimon ,  Ashoke Ravi ,  Nati Dinur

IPC: H03L7/08 ,  H04L27/00 ,  H03L7/085 ,  H03L9/00

Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.

公开(公告)号：US20190068200A1

公开(公告)日：2019-02-28

申请号：US16170716

申请日：2018-10-25

Applicant: Intel IP Corporation

Inventor： Elan Banin ,  Roy Amel ,  Ran Shimon ,  Ashoke Ravi ,  Nati Dinur

IPC: H03L7/08 ,  H04L27/00 ,  H03L7/085

Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.

公开(公告)号：US20180192379A1

公开(公告)日：2018-07-05

申请号：US15828455

申请日：2017-12-01

Applicant: Intel IP Corporation

Inventor： Shahar Gross ,  Ran Shimon ,  Roy Amel ,  Ofer Benjamin ,  Slava Vaysman

IPC: H04W52/52 ,  H04W52/08 ,  H04B17/13 ,  H04B1/04

CPC classification number: H04W52/52 ,  H03F1/00 ,  H04B1/0475 ,  H04B17/13 ,  H04B2001/0416 ,  H04W52/08

Abstract: The present disclosure relates to a transmitter for transmitting a transmit signal comprising a first signal portion and a second signal portion. The transmitter comprises a power amplifier configured to amplify the transmit signal. The power amplifier is prone to undesired gain variations during the first and the second signal portion. The transmitter further comprises a transmit feedback receiver coupled to an output of the power amplifier and configured to feed back the transmit signal to generate a fed back first signal portion and a fed back second signal portion. Processing circuitry is configured to determine a first gain relation between the fed back first signal portion and the first signal portion and to determine at least one second gain relation between the fed back second signal portion and the second signal portion. Power adjustment circuitry is configured to adjust a transmit power of the transmit signal according to a variation between the first gain relation and the second gain relation.

公开(公告)号：US10469036B2

公开(公告)日：2019-11-05

申请号：US15387948

申请日：2016-12-22

Applicant: INTEL IP CORPORATION

Inventor： Ofer Benjamin ,  Shahar Gross ,  Roy Amel

IPC: H03F1/32 ,  H04B1/16 ,  H04B1/04 ,  H04B1/40 ,  H03F3/19 ,  H03G3/30 ,  H04B1/525

Abstract: Methods and systems for calibrating a receiver utilizing a noise signal generated by a power amplifier associated with a transmitter are provided. A calibration method or mode includes generating a noise signal with a power amplifier associated with a transmitter of the transceiver; processing the noise signal with the receiver to generate a received signal; and calibrating the receiver based at least on the received signal.

公开(公告)号：US10181856B2

公开(公告)日：2019-01-15

申请号：US15395504

申请日：2016-12-30

Applicant: Intel IP Corporation

Inventor： Elan Banin ,  Roy Amel ,  Ran Shimon ,  Ashoke Ravi ,  Nati Dinur

IPC: H03L7/08 ,  H04L27/00 ,  H03L7/085

Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.