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公开(公告)号：US09997466B2
公开(公告)日：2018-06-12
申请号：US15352405
申请日：2016-11-15
Applicant: Honeywell International Inc.
Inventor： Eric E. Vogt , Gregor D. Dougal , James L. Tucker
IPC: H01L23/538 , H01L21/48
CPC classification number: H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L23/13 , H01L23/28 , H01L23/3128 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L23/57 , H01L23/573 , H01L24/05 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/05568 , H01L2224/0557 , H01L2224/06181 , H01L2224/08145 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/2919 , H01L2224/32145 , H01L2224/48145 , H01L2224/73253 , H01L2224/73257 , H01L2224/81193 , H01L2224/81203 , H01L2224/81895 , H01L2224/81896 , H01L2224/83805 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2225/06572 , H01L2225/06589 , H01L2924/10253 , H01L2924/14 , H01L2924/1421 , H01L2924/1431 , H01L2924/1436 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/00012
Abstract: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.
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公开(公告)号：US20170125352A1
公开(公告)日：2017-05-04
申请号：US15352405
申请日：2016-11-15
Applicant: Honeywell International Inc.
Inventor： Eric E. Vogt , Gregor D. Dougal , James L. Tucker
IPC: H01L23/538 , H01L21/48
CPC classification number: H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L23/13 , H01L23/28 , H01L23/3128 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L23/57 , H01L23/573 , H01L24/05 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/05568 , H01L2224/0557 , H01L2224/06181 , H01L2224/08145 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/2919 , H01L2224/32145 , H01L2224/48145 , H01L2224/73253 , H01L2224/73257 , H01L2224/81193 , H01L2224/81203 , H01L2224/81895 , H01L2224/81896 , H01L2224/83805 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2225/06572 , H01L2225/06589 , H01L2924/10253 , H01L2924/14 , H01L2924/1421 , H01L2924/1431 , H01L2924/1436 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/00012
Abstract: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.
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3.发明授权Integrated circuit stack including a patterned array of electrically conductive pillars 有权集成电路堆叠，包括导电柱的图案化阵列公开(公告)号：US09548277B2
公开(公告)日：2017-01-17
申请号：US14692154
申请日：2015-04-21
Applicant: Honeywell International Inc.
Inventor： Eric E. Vogt , Gregor D. Dougal , James L. Tucker
CPC classification number: H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L23/13 , H01L23/28 , H01L23/3128 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L23/57 , H01L23/573 , H01L24/05 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/05568 , H01L2224/0557 , H01L2224/06181 , H01L2224/08145 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/2919 , H01L2224/32145 , H01L2224/48145 , H01L2224/73253 , H01L2224/73257 , H01L2224/81193 , H01L2224/81203 , H01L2224/81895 , H01L2224/81896 , H01L2224/83805 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2225/06572 , H01L2225/06589 , H01L2924/10253 , H01L2924/14 , H01L2924/1421 , H01L2924/1431 , H01L2924/1436 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/00012
Abstract: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.
Abstract translation: 本公开描述了一种堆叠集成电路系统，其包括堆叠在插入层的相对侧上的两个集成电路层。 插入层可以包括至少一个集成电路管芯和内插器部分，其包括布置在插入层内的横向图案化阵列中的多个导电柱。
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4.发明申请公开(公告)号：US20160315055A1
公开(公告)日：2016-10-27
申请号：US14692154
申请日：2015-04-21
Applicant: Honeywell International Inc.
Inventor： Eric E. Vogt , Gregor D. Dougal , James L. Tucker
IPC: H01L23/00 , H01L23/498 , H01L25/00 , H01L23/28 , H01L21/56
CPC classification number: H01L23/5389 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/56 , H01L23/13 , H01L23/28 , H01L23/3128 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L23/552 , H01L23/57 , H01L23/573 , H01L24/05 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/05568 , H01L2224/0557 , H01L2224/06181 , H01L2224/08145 , H01L2224/1403 , H01L2224/14181 , H01L2224/16145 , H01L2224/2919 , H01L2224/32145 , H01L2224/48145 , H01L2224/73253 , H01L2224/73257 , H01L2224/81193 , H01L2224/81203 , H01L2224/81895 , H01L2224/81896 , H01L2224/83805 , H01L2225/06513 , H01L2225/06537 , H01L2225/06541 , H01L2225/06572 , H01L2225/06589 , H01L2924/10253 , H01L2924/14 , H01L2924/1421 , H01L2924/1431 , H01L2924/1436 , H01L2924/1461 , H01L2924/15192 , H01L2924/15311 , H01L2924/00012
Abstract: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.
Abstract translation: 本公开描述了一种堆叠集成电路系统，其包括堆叠在插入层的相对侧上的两个集成电路层。 插入层可以包括至少一个集成电路管芯和内插器部分，其包括布置在插入层内的横向图案化阵列中的多个导电柱。
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