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1.发明授权公开(公告)号：US10409766B2
公开(公告)日：2019-09-10
申请号：US15845450
申请日：2017-12-18
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jiangen Liu , Chenghong He , Haibin Wang , Xinyu Hou
IPC: G06F9/30 , G06F15/80 , G06F15/173 , G06F15/167 , G06F13/42
Abstract: A computer subsystem and a computer system, where the computer subsystem includes L composite nodes (CNs), each CN includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller (NC). Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the NC in the basic node. The NC in each basic node has a routing function. Any two NCs in the M basic nodes are interconnected. A connection between the L CNs formed through connections between NCs enables communication between any two NCs to be no more than three hops. Hence, the computer subsystem and the computer system can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.
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2.发明申请Method, Apparatus, and System for Retransmitting Data Packet in Quick Path Interconnect System 有权快速路径互连系统中重传数据包的方法，装置和系统公开(公告)号：US20140108878A1
公开(公告)日：2014-04-17
申请号：US14107109
申请日：2013-12-16
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jiangen Liu , Gang Liu , Weiguang Cai
IPC: H04L1/08
CPC classification number: H04L1/08 , H04L1/16 , H04L1/1809 , H04L1/1816 , H04L69/40 , H04L2001/0094
Abstract: The present invention discloses a method for retransmitting a data packet in a quick path interconnect system, and a node. When a first node serves as a sending end, only the first data packet detected to be faulty is retransmitted to a second node, thereby saving system resources that need to be occupied in the data packet retransmission. When the first node serves as a receiving end, it implements that the packet loss does not occur in the first node in a case that the second node only retransmits the second data packet detected to be faulty, thereby ensuring reliability of the data packet transmission based on the QPI bus.
Abstract translation: 本发明公开了一种在快速路径互连系统和节点中重传数据分组的方法。 当第一节点用作发送端时，只有检测到有故障的第一数据包被重传到第二节点，从而节省了在数据分组重传中需要占用的系统资源。 当第一节点用作接收端时，在第二节点仅重发检测到的第二数据包有故障的情况下，实现在第一节点中不发生分组丢失，从而确保基于数据分组传输的可靠性 在QPI总线上
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3.发明申请COMPUTER SUBSYSTEM AND COMPUTER SYSTEM WITH COMPOSITE NODES IN AN INTERCONNECTION STRUCTURE 审中-公开计算机子系统与计算机系统与互连结构中的复合节点公开(公告)号：US20160328357A1
公开(公告)日：2016-11-10
申请号：US15150419
申请日：2016-05-09
Applicant: HUAWEI TECHNOLOGIES CO.,LTD.
Inventor： Jiangen Liu , Chenghong He , Haibin Wang , Xinyu Hou
CPC classification number: G06F15/80 , G06F13/4221 , G06F15/167 , G06F15/17337
Abstract: The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller. Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the node controller in the basic node. The node controller in each basic node has a routing function. Any two node controllers in the M basic nodes are interconnected. A connection between the L composite nodes formed through connections between node controllers enables communication between any two node controllers to be no more than three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.
Abstract translation: 本发明提供一种计算机子系统和计算机系统。 计算机子系统包括L个复合节点，每个复合节点包括M个基本节点，每个基本节点包括N个中央处理单元（CPU）和一个节点控制器。 每个基本节点中的任何两个CPU都是互连的。 每个基本节点中的每个CPU都连接到基本节点中的节点控制器。 每个基本节点中的节点控制器具有路由功能。 M个基本节点中的任何两个节点控制器互连。 通过节点控制器之间的连接形成的L个复合节点之间的连接使得任何两个节点控制器之间的通信不超过三跳。 根据本发明的实施例的计算机子系统和计算机系统可以减少互连芯片的种类和数量，并且简化系统的互连结构，从而提高系统的可靠性。
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4.发明授权Method, apparatus, and system for retransmitting data packet in quick path interconnect system 有权用于在快速路径互连系统中重传数据包的方法，装置和系统公开(公告)号：US09197373B2
公开(公告)日：2015-11-24
申请号：US14107109
申请日：2013-12-16
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jiangen Liu , Gang Liu , Weiguang Cai
CPC classification number: H04L1/08 , H04L1/16 , H04L1/1809 , H04L1/1816 , H04L69/40 , H04L2001/0094
Abstract: The present invention discloses a method for retransmitting a data packet in a quick path interconnect system, and a node. When a first node serves as a sending end, only the first data packet detected to be faulty is retransmitted to a second node, thereby saving system resources that need to be occupied in the data packet retransmission. When the first node serves as a receiving end, it implements that the packet loss does not occur in the first node in a case that the second node only retransmits the second data packet detected to be faulty, thereby ensuring reliability of the data packet transmission based on the QPI bus.
Abstract translation: 本发明公开了一种在快速路径互连系统和节点中重传数据分组的方法。 当第一节点用作发送端时，只有检测到有故障的第一数据包被重传到第二节点，从而节省了在数据分组重传中需要占用的系统资源。 当第一节点用作接收端时，在第二节点仅重发检测到的第二数据包有故障的情况下，实现第一节点中不发生分组丢失，从而确保基于数据分组传输的可靠性 在QPI总线上。
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5.发明授权公开(公告)号：US09880972B2
公开(公告)日：2018-01-30
申请号：US15150419
申请日：2016-05-09
Applicant: HUAWEI TECHNOLOGIES CO., LTD.
Inventor： Jiangen Liu , Chenghong He , Haibin Wang , Xinyu Hou
IPC: G06F9/30 , G06F15/80 , G06F15/173 , G06F15/167 , G06F13/42
CPC classification number: G06F15/80 , G06F13/4221 , G06F15/167 , G06F15/17337
Abstract: The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller. Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the node controller in the basic node. The node controller in each basic node has a routing function. Any two node controllers in the M basic nodes are interconnected. A connection between the L composite nodes formed through connections between node controllers enables communication between any two node controllers to be no more than three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.
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Patent Agency Ranking
公开(公告)号：US09465743B2
公开(公告)日：2016-10-11
申请号：US13719626
申请日：2012-12-19
Applicant: Huawei Technologies Co., Ltd.
Inventor： Wei Zheng , Jiangen Liu , Gang Liu , Weiguang Cai
CPC classification number: G06F12/084 , G06F12/0806 , G06F12/0811 , G06F2212/1012
Abstract: Embodiments of the present invention disclose a method for accessing a cache and a pseudo cache agent (PCA). The method of the present invention is applied to a multiprocessor system, where the system includes at least one NC, at least one PCA conforming to a processor micro-architecture level interconnect protocol is embedded in the NC, the PCA is connected to at least one PCA storage device, and the PCA storage device stores data shared among memories in the multiprocessor system. The method of the present invention includes: if the NC receives a data request, obtaining, by the PCA, target data required in the data request from the PCA storage device connected to the PCA; and sending the target data to a sender of the data request. Embodiments of the present invention are mainly applied to a process of accessing cache data in the multiprocessor system.
Abstract translation: 本发明的实施例公开了一种用于访问高速缓存和伪高速缓存代理（PCA）的方法。 本发明的方法应用于多处理器系统，其中系统包括至少一个NC，至少一个符合处理器微架构级互连协议的PCA嵌入在NC中，PCA连接到至少一个 PCA存储装置，PCA存储装置将存储在多处理器系统中的数据共享。 本发明的方法包括：如果NC接收到数据请求，则由PCA从连接到PCA的PCA存储设备获得数据请求中所需的目标数据; 并将目标数据发送到数据请求的发送者。 本发明的实施例主要应用于在多处理器系统中访问高速缓存数据的过程。
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7.发明授权Computer subsystem and computer system with composite nodes in an interconnection structure 有权具有互连结构中复合节点的计算机子系统和计算机系统公开(公告)号：US09336179B2
公开(公告)日：2016-05-10
申请号：US13670718
申请日：2012-11-07
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jiangen Liu , Chenghong He , Haibin Wang , Xinyu Hou
IPC: G06F9/30 , G06F15/173 , G06F15/167
CPC classification number: G06F15/80 , G06F13/4221 , G06F15/167 , G06F15/17337
Abstract: The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units CPUs and one node controller NC, where any two CPUs in each basic node are interconnected, each CPU in each basic node is connected to the NC in the basic node, the NC in each basic node has a routing function, any two NCs in the M basic nodes are interconnected, and a connection between the L composite nodes formed through a connection between NCs enable communication between any two NCs to require at most three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.
Abstract translation: 本发明提供一种计算机子系统和计算机系统。 计算机子系统包括L个复合节点，每个复合节点包括M个基本节点，每个基本节点包括N个中央处理单元CPU和一个节点控制器NC，其中每个基本节点中的任何两个CPU互连，每个基本节点中的每个CPU都连接 在基本节点中的NC中，每个基本节点中的NC具有路由功能，M个基本节点中的任何两个NC互连，并且通过NC之间的连接形成的L个复合节点之间的连接使得任何两个NC之间的通信 要求最多三跳。 根据本发明的实施例的计算机子系统和计算机系统可以减少互连芯片的种类和数量，并且简化系统的互连结构，从而提高系统的可靠性。
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8.发明申请公开(公告)号：US20180107628A1
公开(公告)日：2018-04-19
申请号：US15845450
申请日：2017-12-18
Applicant: Huawei Technologies Co., Ltd.
Inventor： Jiangen Liu , Chenghong He , Haibin Wang , Xinyu Hou
IPC: G06F15/80 , G06F15/173 , G06F15/167 , G06F13/42
CPC classification number: G06F15/80 , G06F13/4221 , G06F15/167 , G06F15/17337
Abstract: A computer subsystem and a computer system, where the computer subsystem includes L composite nodes (CNs), each CN includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller (NC). Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the NC in the basic node. The NC in each basic node has a routing function. Any two NCs in the M basic nodes are interconnected. A connection between the L CNs formed through connections between NCs enables communication between any two NCs to be no more than three hops. Hence, the computer subsystem and the computer system can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.
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9.发明授权Node routing method of multi-processor system, controller and multi-processor system 有权多处理器系统，控制器和多处理器系统的节点路由方法公开(公告)号：US09300527B2
公开(公告)日：2016-03-29
申请号：US14084393
申请日：2013-11-19
Applicant: Huawei Technologies Co., Ltd.
Inventor： Haibin Wang , Jiangen Liu
IPC: G01R31/08 , H04L12/24 , H04L12/64 , H04L29/08 , H04L12/437 , H04L12/715 , H04L12/703
CPC classification number: H04L41/0654 , H04L12/437 , H04L12/6418 , H04L45/04 , H04L45/28 , H04L69/324
Abstract: The present invention provides a node routing method of a multi-processor system, a controller and a multi-processor system. The method includes learning a state of an available link between nodes in the multi-processor system, where the multi-processor system includes a first subnet and the first subnet includes at least two connected nodes, and when at least one link in the first subnet fails, reselecting an available link between all nodes in the first subnet, so that the nodes in the first subnet use the reselected available link to route a packet, where the reselected available link is a link on each node in the first subnet except a link whose dimension sequence number is the same as that of the failed link, a dimension sequence number is numbers of a link at two end nodes, and numbers of a link at two end nodes are the same.
Abstract translation: 本发明提供了多处理器系统，控制器和多处理器系统的节点路由方法。 该方法包括学习多处理器系统中的节点之间的可用链路的状态，其中多处理器系统包括第一子网，并且第一子网包括至少两个连接的节点，以及当第一子网中的至少一个链路 失败，重新选择第一子网中的所有节点之间的可用链接，使得第一子网中的节点使用重新选择的可用链路来路由分组，其中重新选择的可用链路是第一子网中的每个节点上的链路，除了链路 其维度序列号与故障链路的序列号相同，维度序列号是两端节点的链路数，两端节点的链路数量相同。
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10.发明申请Node Routing Method of Multi-Processor System, Controller and Multi-Processor System 有权多处理器系统，控制器和多处理器系统的节点路由方法公开(公告)号：US20140078891A1
公开(公告)日：2014-03-20
申请号：US14084393
申请日：2013-11-19
Applicant: Huawei Technologies Co., Ltd.
Inventor： Haibin Wang , Jiangen Liu
CPC classification number: H04L41/0654 , H04L12/437 , H04L12/6418 , H04L45/04 , H04L45/28 , H04L69/324
Abstract: The present invention provides a node routing method of a multi-processor system, a controller and a multi-processor system. The method includes learning a state of an available link between nodes in the multi-processor system, where the multi-processor system includes a first subnet and the first subnet includes at least two connected nodes, and when at least one link in the first subnet fails, reselecting an available link between all nodes in the first subnet, so that the nodes in the first subnet use the reselected available link to route a packet, where the reselected available link is a link on each node in the first subnet except a link whose dimension sequence number is the same as that of the failed link, a dimension sequence number is numbers of a link at two end nodes, and numbers of a link at two end nodes are the same.
Abstract translation: 本发明提供了多处理器系统，控制器和多处理器系统的节点路由方法。 该方法包括学习多处理器系统中的节点之间的可用链路的状态，其中多处理器系统包括第一子网，并且第一子网包括至少两个连接的节点，以及当第一子网中的至少一个链路 失败，重新选择第一子网中的所有节点之间的可用链接，使得第一子网中的节点使用重新选择的可用链路来路由数据包，其中重新选择的可用链路是第一子网中除了链路之外的每个节点上的链路 其维度序列号与故障链路的序列号相同，维度序列号是两端节点的链路数，两端节点的链路数量相同。
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