公开(公告)号：US20230037617A1

公开(公告)日：2023-02-09

申请号：US17972689

申请日：2022-10-25

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Jiantao ZHENG ,  Nan ZHAO ,  Shanghsuan CHIANG ,  Yu JIANG ,  Jianbiao LU ,  Yiwei REN

IPC: H01L23/433 ,  H01L23/367 ,  H01L23/29 ,  H01L21/52 ,  H01L21/56

Abstract: A chip is mounted on a surface of the substrate, and the thermally conductive cover is disposed on a side that is of the chip and that is away from the substrate. There is a filling area on a surface that is of the thermally conductive cover and that faces the substrate, and the filling area is opposite to the chip. There is an accommodation cavity whose opening faces the substrate in the filling area. A thermal interface material layer is filled between the chip and a bottom surface of the accommodation cavity. Between an opening edge of the accommodation cavity and the substrate, there is a first gap connected to the accommodation cavity. The filling material encircles a side surface of the thermal interface material layer, so that the filling material separates the side surface of the thermal interface material layer from air.

公开(公告)号：US20200381361A1

公开(公告)日：2020-12-03

申请号：US16997003

申请日：2020-08-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Nan ZHAO ,  Wenxu XIE ,  Junlei TAO ,  Shanghsuan CHIANG ,  HuiLi FU

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.

公开(公告)号：US20240178187A1

公开(公告)日：2024-05-30

申请号：US18430903

申请日：2024-02-02

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Shanghsuan CHIANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/0801 ,  H01L2224/08146 ,  H01L2224/16014 ,  H01L2224/16146 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L2924/3511

Abstract: A chip package structure includes: a substrate, a first connection chip, conductive columns, a first packaging layer, a first chip, and a second chip. The first connection chip is disposed on the substrate. The conductive columns is disposed on the substrate and located on a periphery of the first connection chip. The first packaging layer is disposed on the substrate and wrapping the first connection chip and the conductive columns, with the active surface of the first connection chip and top surfaces of the conductive columns exposed. The first chip is disposed on the first packaging layer, and coupled to both the conductive columns and the first connection chip. The second chip is disposed on the first packaging layer and that is away from the substrate, and coupled to both the conductive columns and the first connection chip.

公开(公告)号：US20220278056A1

公开(公告)日：2022-09-01

申请号：US17746186

申请日：2022-05-17

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Nan ZHAO ,  Chunghsuan TSAI ,  Shanghsuan CHIANG

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

Abstract: A chip package includes a substrate, a first die, a second die, and a beam structure. The first die and the second die are disposed on a side of the substrate and are electrically connected to the substrate. The beam structure is disposed between the first die and the second die. A first end of the beam structure is stacked with and fixedly connected to a part of the first die, a second end is stacked with and fixedly connected to a part of the second die, and the beam structure is insulated from and connected to the first die and the second die. A thermal expansion coefficient of the beam structure is less than a thermal expansion coefficient of the substrate.

公开(公告)号：US20220020659A1

公开(公告)日：2022-01-20

申请号：US17489403

申请日：2021-09-29

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jiantao ZHENG ,  Nan ZHAO ,  Shanghsuan CHIANG ,  Xiao HU ,  Junlei TAO ,  Yu JIANG ,  Jianbiao LU

IPC: H01L23/367 ,  H01L23/053 ,  H01L23/373 ,  H01L21/52

Abstract: Embodiments of this application disclose a packaged chip and a method for manufacturing a packaged chip. The packaged chip includes a substrate, a chip, and a heat sink. The heat sink includes a first bracket, a second bracket, and a cover. The first bracket and the second bracket are disposed on the substrate. The cover is supported on the substrate by the first bracket and the second bracket. The first bracket is a sealed annular bracket. The first bracket and the cover encircle a first space. The chip is accommodated in the first space. A thermal interface material is disposed between the chip and the cover. A hole connected to the first space is provided on the cover. The hole and the first space are filled with a filling material. The second bracket is located outside the first space.