PACKAGED CHIP AND METHOD FOR MANUFACTURING PACKAGED CHIP

    公开(公告)号:US20220020659A1

    公开(公告)日:2022-01-20

    申请号:US17489403

    申请日:2021-09-29

    Abstract: Embodiments of this application disclose a packaged chip and a method for manufacturing a packaged chip. The packaged chip includes a substrate, a chip, and a heat sink. The heat sink includes a first bracket, a second bracket, and a cover. The first bracket and the second bracket are disposed on the substrate. The cover is supported on the substrate by the first bracket and the second bracket. The first bracket is a sealed annular bracket. The first bracket and the cover encircle a first space. The chip is accommodated in the first space. A thermal interface material is disposed between the chip and the cover. A hole connected to the first space is provided on the cover. The hole and the first space are filled with a filling material. The second bracket is located outside the first space.

    CHIP AND PACKAGING METHOD
    2.
    发明申请

    公开(公告)号:US20200381361A1

    公开(公告)日:2020-12-03

    申请号:US16997003

    申请日:2020-08-19

    Abstract: A chip and a packaging method thereof. In the chip, first solder pads in a first solder pad array on a first substrate are attached to corresponding second pins in second pin arrays on different dies to implement short-distance and high-density interconnection of the different dies. A molding body is used to wrap a first pin, a second pin, a first solder pad, and the first substrate, so that a fan-out unit and the first substrate are molded into an integral structure. In the integral structure, bottoms of first pins that are in a first pin array on a die and that are electrically connected to a periphery of the chip are not wrapped by the molding body.

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