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公开(公告)号：US09105726B2
公开(公告)日：2015-08-11
申请号：US14192239
申请日：2014-02-27
Inventor： Sung Haeng Cho , Sang-Hee Park , Chi-Sun Hwang
IPC: H01L29/786 , H01L29/66 , H01L29/417
CPC classification number: H01L29/41775 , H01L29/0847 , H01L29/41733 , H01L29/41758 , H01L29/66742 , H01L29/66969 , H01L29/786 , H01L29/78603 , H01L29/7869
Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.
Abstract translation: 提供一种晶体管。 晶体管包括：衬底; 半导体层，其设置在所述基板上，并且具有与所述基板垂直的一侧，所述另一侧面向所述一侧; 沿所述基板延伸并接触所述半导体层的一侧的第一电极; 第二电极，沿着衬底延伸并接触半导体层的另一侧; 布置在所述第一电极上并与所述第二电极间隔开的导线; 设置在所述半导体层上的栅电极; 以及设置在所述半导体层和所述栅电极之间的栅绝缘层，其中所述半导体层，所述第一电极和所述第二电极具有共面。
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公开(公告)号：US09035688B2
公开(公告)日：2015-05-19
申请号：US14010579
申请日：2013-08-27
Applicant: Konkuk University Industrial Cooperation Corp. , Electronics and Telecommunications Research Institute
Inventor： Jae-Eun Pi , Kee-Chan Park , Sangyeon Kim , Joondong Kim , Yeon Kyung Kim , HongKyun Lym , Sang-Hee Park , Byoung Gon Yu , Chi-Sun Hwang , Jong Woo Kim , OhSang Kwon , Min Ki Ryu
IPC: H03L5/00 , H03K17/30 , H03K19/0185
CPC classification number: H03K17/302 , H03K19/0185
Abstract: Provided is a single input level shifter. The single input level shifter includes: an input unit applying a power voltage to a first node in response to an input signal and applying the input signal to a second node in response to a reference signal; a bootstrapping unit applying the power voltage to the second node according to a voltage level of the first node; and an output unit applying the input signal to an output terminal in response to the reference signal and applying the power voltage to the output terminal according to the voltage level of the first node, wherein the bootstrapping unit includes a capacitor between the first and second nodes, and when the input signal is shifted from a first voltage level to a second voltage level, the bootstrapping unit raises the voltage level of the first node to a level higher than the power voltage.
Abstract translation: 提供单个输入电平移位器。 单输入电平移位器包括：输入单元，响应于输入信号向第一节点施加电源电压，并响应于参考信号将输入信号施加到第二节点; 引导单元，根据第一节点的电压电平向第二节点施加电源电压; 以及输出单元，其响应于所述参考信号将输入信号施加到输出端子，并且根据所述第一节点的电压电平将所述电源电压施加到所述输出端子，其中所述自举单元包括所述第一和第二节点之间的电容器 并且当所述输入信号从第一电压电平偏移到第二电压电平时，所述自举单元将所述第一节点的电压电平升高到高于所述电源电压的电平。
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公开(公告)号：US09252222B2
公开(公告)日：2016-02-02
申请号：US14800251
申请日：2015-07-15
Inventor： Sung Haeng Cho , Sang-Hee Park , Chi-Sun Hwang
IPC: H01L29/417 , H01L29/66 , H01L29/08 , H01L29/786
CPC classification number: H01L29/41775 , H01L29/0847 , H01L29/41733 , H01L29/41758 , H01L29/66742 , H01L29/66969 , H01L29/786 , H01L29/78603 , H01L29/7869
Abstract: Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.
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