公开(公告)号：US09824017B2

公开(公告)日：2017-11-21

申请号：US14253349

申请日：2014-04-15

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho Han ,  Young Su Kwon ,  Kyoung Seon Shin

IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0831

CPC classification number: G06F12/0875 ,  G06F12/0831 ,  G06F12/0833

Abstract: Provided is a cache control apparatus and method that, when a plurality of processors read a program from the same memory in a chip, maintain coherency of data and an instruction generated by a cache memory. The cache control apparatus includes a coherency controller client configured to include an MESI register, which is included in an instruction cache, and stores at least one of a modified state, an exclusive state, a shared state, and an invalid state for each line of the instruction cache, and a coherency interface connected to the coherency controller and configured to transmit and receive broadcast address information, read or write information, and hit or miss information of another cache to and from the instruction cache.

公开(公告)号：US10013310B2

公开(公告)日：2018-07-03

申请号：US15241808

申请日：2016-08-19

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Ho Han ,  Young-Su Kwon ,  Kyoung Seon Shin ,  Kyung Jin Byun ,  Nak Woong Eum

IPC: G06F11/10 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0895

CPC classification number: G06F11/1076 ,  G06F11/1044 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/1032 ,  Y02D10/13

Abstract: Provided is an operating method of a cache memory device includes receiving an address from an external device, reading an entry corresponding to at least a portion of the received address among a plurality of entries that are included in the cache memory, performing error detection on additional information that is included in the read entry, and performing a recovery operation on the entry based on a result of error detection and the additional information. The entry includes the additional information and a cache line corresponding to the additional information, and the additional information includes a tag, valid bit, and dirty bit that correspond to the cache line.

公开(公告)号：US20180165246A1

公开(公告)日：2018-06-14

申请号：US15832824

申请日：2017-12-06

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jin Ho Han ,  Kyoung Seon Shin ,  Young-Su Kwon

IPC: G06F15/80 ,  G06F9/30 ,  G06F12/0842 ,  G06F11/07

Abstract: A multi-core processor having a first operation mode in which processors perform the same task and a second operation mode in which the processors perform different tasks includes first and second processors configured to write an operation mode value to a first register or second register when a function called in executed software requests the first or second operation mode, a manager configured to assign core IDs of the first and second processors according to the operation mode value stored in the first register or second register, and a reset controller configured to reset the first and second processors in response to the function, wherein the manager assigns the same core ID to the first and second processors when the operation mode value indicates the first operation mode, and allocates different core IDs to the first and second processors when the operation mode value indicates the second operation mode.