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公开(公告)号：US20230168936A1
公开(公告)日：2023-06-01
申请号：US17980008
申请日：2022-11-03
Inventor： Jaehoon CHUNG , Young-Su KWON , Jin Ho HAN
IPC: G06F9/50
CPC classification number: G06F9/5027
Abstract: A method and apparatus for allocating tasks through relocating kernel data based on a size of systolic array included in each of the plurality of processors, and relocating input feature map (IFM) data based on a number of the plurality of processors are provided.
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公开(公告)号：US20170222648A1
公开(公告)日：2017-08-03
申请号：US15414236
申请日：2017-01-24
Inventor： Woojoo LEE , Young-Su KWON , Kyung Jin BYUN , Jin Ho HAN , Nak Woong EUM
IPC: H03K19/00
CPC classification number: H03K19/0013 , G06F3/0202 , H01L27/1104 , H01L29/49 , H03K17/9638 , H03K19/00369 , H03K19/0944
Abstract: An Ultra Low Voltage (ULV) digital circuit includes a logic circuit comprising a plurality of logic gates and a plurality of buffered interconnects for connecting between the plurality of logic gates, a temperature sensor configured to detect a temperature of the logic circuit, and a voltage controller configured to control a driving voltage provided to the logic circuit in order to reduce a power consumption of the logic circuit based on the detected temperature. Each of the plurality of logic gates and buffered interconnects reduces a signal delay as a temperature increases.
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公开(公告)号：US20150149836A1
公开(公告)日：2015-05-28
申请号：US14547301
申请日：2014-11-19
Inventor： Young Su KWON , Jin Ho HAN , Kyung Jin BYUN
IPC: G06F11/07
CPC classification number: G06F11/0772 , G06F11/0721 , G06F11/183
Abstract: A recoverable and fault-tolerant CPU core and a control method thereof are provided. The recoverable and fault-tolerant CPU core includes first, second, and third arithmetic logic circuits configured to perform a calculation requested by the same instruction, a first selector configured to compare calculation values output from the first, second, and third arithmetic logic circuits by the same instruction, determine as a normal state when two or more of the calculation values are the same, and if not, determine as a fault state, and a register file configured to record the calculation value having the same value, when determining as the normal state in the first selector.
Abstract translation: 提供了一种可恢复和容错的CPU内核及其控制方法。 可恢复和容错CPU核心包括被配置为执行由相同指令请求的计算的第一，第二和第三算术逻辑电路，第一选择器被配置为将从第一，第二和第三算术逻辑电路输出的计算值与 相同的指令，当两个或多个计算值相同时确定为正常状态，如果不是，则确定为故障状态，以及配置为记录具有相同值的计算值的寄存器文件，当确定为 第一选择器中的正常状态。
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公开(公告)号：US20230147293A1
公开(公告)日：2023-05-11
申请号：US17983016
申请日：2022-11-08
Inventor： Min-Hyung CHO , Young-Deuk JEON , Jin Ho HAN
IPC: G11C11/4099 , G11C5/06 , G11C5/04
CPC classification number: G11C11/4099 , G11C5/063 , G11C5/04
Abstract: A method for ZQ calibration for a data transmission driving circuit of each memory die in a memory chip package in which memory dies are stacked, includes generating a reference current through a reference resistor connected between a power terminal supplying a power voltage of the data transmission driving circuit and a ground terminal and a first transistor that is diode-connected; supplying first currents corresponding to the reference currents to a pull-up driver of each memory die; performing ZQ calibration of a pull-up driver of a corresponding memory die by comparing a first voltage formed by each first current with a reference voltage formed by the reference current in each of the plurality of memory dies; and performing ZQ calibration of a pull-down driver of the corresponding memory die based on an output impedance of the ZQ calibrated pull-up driver in each of the memory dies.
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公开(公告)号：US20220164192A1
公开(公告)日：2022-05-26
申请号：US17533788
申请日：2021-11-23
Inventor： Chun-Gi LYUH , Hyun Mi KIM , Young-Su KWON , Jin Ho HAN
Abstract: Disclosed is a parallel processor. The parallel processor includes a processing element array including a plurality of processing elements arranged in rows and columns, a row memory group including row memories corresponding to rows of the processing elements, a column memory group including column memories corresponding to columns of the processing elements, and a controller to generate a first address and a second address, to send the first address to the row memory group, and to send the second address to the column memory group. The controller supports convolution operations having mutually different forms, by changing a scheme of generating the first address.
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Patent Agency Ranking
公开(公告)号：US20200167245A1
公开(公告)日：2020-05-28
申请号：US16694913
申请日：2019-11-25
Inventor： Jin Ho HAN , Young-Su KWON , Min-Seok CHOI
Abstract: Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.
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公开(公告)号：US20190108105A1
公开(公告)日：2019-04-11
申请号：US16117403
申请日：2018-08-30
Inventor： Jin Ho HAN , Min-Seok CHOI , Young-Su KWON
IPC: G06F11/14
Abstract: Provided is a semiconductor system including: a fault detector configured to obtain fault information related to a fault occurring in a first intellectual property (IP); a fault manager configured to store recovery information providing one or more recovery methods related to the fault information and determine a recovery method for recovering the fault occurring in the first IP among the one or more recovery methods based on the recovery information; and a fault recovery module configured to control the first IP based on the determined recovery method. The determined recovery method involves communication between the first IP and a second IP and the fault occurring in the first IP is recovered based on data delivered according to the communication between the first IP and the second IP.
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公开(公告)号：US20150143045A1
公开(公告)日：2015-05-21
申请号：US14253466
申请日：2014-04-15
Inventor： Jin Ho HAN , Young Su KWON , Kyoung Seon SHIN
IPC: G06F12/08
CPC classification number: G06F12/0897 , G06F12/0862 , G06F2212/1021 , G06F2212/6022
Abstract: Provided are a cache control apparatus and method for reducing a miss penalty. The cache control apparatus includes a first level cache configured to store data in a memory, a second level cache connected to the first level cache, and configured to be accessed by a processor when the first level cache fails to call data according to a data request instruction, a prefetch buffer connected to the first and second level caches, and configured to temporarily store data transferred from the first and second level caches to a core, and a write buffer connected to the first level cache, and configured to receive address information and data of the first level cache.
Abstract translation: 提供了一种用于减少未命中罚款的高速缓存控制装置和方法。 高速缓存控制装置包括被配置为将数据存储在存储器中的第一级高速缓存，连接到第一级高速缓存的第二级高速缓存，并且被配置为当第一级高速缓存不能根据数据请求调用数据时被处理器访问 指令，连接到第一和第二级高速缓存的预取缓冲器，并且被配置为将从第一和第二级别高速缓存传送的数据临时存储到核心，以及连接到第一级高速缓存的写缓冲器，并且被配置为接收地址信息和 第一级缓存的数据。
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公开(公告)号：US20220172029A1
公开(公告)日：2022-06-02
申请号：US17536536
申请日：2021-11-29
Inventor： In San JEON , Young-Su KWON , Chun-Gi LYUH , Young-deuk JEON , MIN-HYUNG CHO , Jin Ho HAN
Abstract: Disclosed is a simplified sigmoid function circuit which includes a first circuit that performs a computation on input data based on a simplified sigmoid function when a sign of a real region of the input data is positive, a second circuit that performs the computation on the input data based on the simplified sigmoid function when the sign of the real region of the input data is negative, and a first multiplexer that selects and output one of an output of the first circuit and an output of the second circuit, based on the sign of the input data. The simplified sigmoid function is obtained by transforming a sigmoid function of a real region into a sigmoid function of a logarithmic region and performing a variational transformation for the sigmoid function of the logarithmic region.
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公开(公告)号：US20220171631A1
公开(公告)日：2022-06-02
申请号：US17538147
申请日：2021-11-30
Inventor： Ju-Yeob KIM , Jin Ho HAN
IPC: G06F9/38
Abstract: A method for processing floating point operations in a multi-processor system including a plurality of single processor cores is provided. In this method, upon receiving a group setting for performing an operation, the plurality of single processor cores are grouped into at least one group according to the group setting, and a single processor core set as a master in the group loads an instruction for performing the operation from an external memory, and performs parallel operations by utilizing floating point units (FUPs) of all single processor cores in the group according to the instructions.
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