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1.发明申请BIAS SENSING IN DRAM SENSE AMPLIFIERS THROUGH VOLTAGE-COUPLING/DECOUPLING DEVICE 有权通过电压耦合/解耦器件对DRAM感应放大器进行偏置感测公开(公告)号：US20110157962A1
公开(公告)日：2011-06-30
申请号：US13039169
申请日：2011-03-02
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.
摘要翻译： 在DRAM器件内提供电压耦合/去耦装置，用于改善读出放大器的偏置感测，从而改善刷新性能。 电压耦合/解耦装置将耦合到读出放大器的相应数字线耦合或去耦偏置电压。 通过从数字线耦合和解耦电压，可以提高刷新操作之间的时间间隔。
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2.发明申请Bias Sensing in Dram Sense Amplifiers Through Voltage-Coupling/Decoupling Device 有权通过电压耦合/去耦装置的感测放大器中的偏置感测公开(公告)号：US20090323448A1
公开(公告)日：2009-12-31
申请号：US12498541
申请日：2009-07-07
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.
摘要翻译： 在DRAM器件内提供电压耦合/去耦装置，用于改善读出放大器的偏置感测，从而改善刷新性能。 电压耦合/解耦装置将耦合到读出放大器的相应数字线耦合或去耦偏置电压。 通过从数字线耦合和解耦电压，可以提高刷新操作之间的时间间隔。
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3.发明授权Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device 有权通过电压耦合/去耦器件在DRAM读出放大器中进行偏置感测公开(公告)号：US08767496B2
公开(公告)日：2014-07-01
申请号：US13039169
申请日：2011-03-02
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.
摘要翻译： 在DRAM器件内提供电压耦合/去耦装置，用于改善读出放大器的偏置感测，从而改善刷新性能。 电压耦合/解耦装置将耦合到读出放大器的相应数字线耦合或去耦偏置电压。 通过从数字线耦合和解耦电压，可以提高刷新操作之间的时间间隔。
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4.发明授权Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device 有权通过电压耦合/去耦器件在DRAM读出放大器中进行偏置感测公开(公告)号：US07903488B2
公开(公告)日：2011-03-08
申请号：US12498541
申请日：2009-07-07
IPC分类号： G11C7/00
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.
摘要翻译： 在DRAM器件内提供电压耦合/去耦装置，用于改善读出放大器的偏置感测，从而改善刷新性能。 电压耦合/解耦装置将耦合到读出放大器的相应数字线耦合或去耦偏置电压。 通过从数字线耦合和解耦电压，可以提高刷新操作之间的时间间隔。
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公开(公告)号：US06757202B2
公开(公告)日：2004-06-29
申请号：US10233871
申请日：2002-08-29
IPC分类号： G11C1604
CPC分类号： G11C11/4091 , G11C7/065 , G11C7/12 , G11C11/4094 , G11C2207/005
摘要： Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased.
摘要翻译： 在DRAM器件内提供电压耦合/去耦装置，用于改善读出放大器的偏置感测，从而改善刷新性能。 电压耦合/解耦装置将耦合到读出放大器的相应数字线耦合或去耦偏置电压。 通过从数字线耦合和解耦电压，可以提高刷新操作之间的时间间隔。
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6.发明授权System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices 有权用于在动态随机存取存储器件的扩展刷新周期期间降低功耗的系统和方法公开(公告)号：US07995415B2
公开(公告)日：2011-08-09
申请号：US12082579
申请日：2008-04-11
申请人： Stephen L. Casper
发明人： Stephen L. Casper
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/1006 , G11C7/1078 , G11C11/40615 , G11C11/4074 , G11C11/4096 , G11C2211/4067 , G11C2211/4068
摘要： A dynamic random access memory (“DRAM”) device is operable in either a normal refresh mode or a static refresh mode, such as a self-refresh mode. A cell plate voltage selector couples a voltage of one-half the supply voltage to the cell plate of a DRAM array in a normal refresh mode and in the static refresh mode when memory cells are being refreshed. In between refresh bursts in the static refresh mode, the cell plate voltage selector couples a reduced voltage to the cell plate. This reduces the voltage reduces the voltage across diode junctions formed between the source/drain of respective access transistor and the substrate. The reduced voltage reduces the discharge current flowing from memory cells capacitors, thereby allowing a reduction in the required refresh rate and a consequential reduction in power consumption.
摘要翻译： 动态随机存取存储器（“DRAM”）设备可以在正常刷新模式或静态刷新模式（诸如自刷新模式）中操作。 电池板电压选择器将正常刷新模式下的电源电压的一半电压与DRAM阵列的单元板耦合，并且当刷新存储器单元时，静态刷新模式。 在静态刷新模式下的刷新突发之间，单元板电压选择器将降低的电压耦合到单元板。 这降低了形成在各个存取晶体管的源极/漏极与衬底之间的二极管结上的电压。 降低的电压降低了从存储单元电容器流出的放电电流，从而允许减少所需的刷新率并因此降低功耗。
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公开(公告)号：US06922368B2
公开(公告)日：2005-07-26
申请号：US10820406
申请日：2004-04-08
申请人： Stephen L. Casper
发明人： Stephen L. Casper
IPC分类号： F01D5/30 , F01D9/04 , G11C7/20 , G11C11/4072 , G11C7/00
CPC分类号： G11C11/4072 , G11C7/20
摘要： A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.
摘要翻译： 在初始施加电力时减少启用动态随机存取存储器（DRAM）的时间的方法和装置包括在初始上电时产生内部RAS信号以产生内部电压。 在短时间延迟结束后，内部RAS脉冲被置位。 在内部RAS脉冲被置位之后，数字线对上的电压用读出放大器放大。 然后，数字线对上的放大电压用平衡电路平衡。 平衡电压也通过平衡电路耦合以对存储单元电容器的公共板充电。
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公开(公告)号：US06760264B2
公开(公告)日：2004-07-06
申请号：US10224950
申请日：2002-08-20
申请人： Stephen L. Casper
发明人： Stephen L. Casper
IPC分类号： G11C700
CPC分类号： G11C11/4072 , G11C7/20
摘要： A method and apparatus of reducing the time for enabling a dynamic random access memory (DRAM) upon initial application of power, comprises generating an internal RAS signal upon initial power up to generate internal voltages. The internal RAS pulse is asserted after a short time delay ends. After the internal RAS pulse is asserted, voltages on a digit line pair are amplified with a sense amplifier. Then, the amplified voltages on the digit line pair are equilibrated with an equilibration circuit. The equilibrated voltage is also coupled through the equilibration circuit to charge a common plate of a memory cell capacitor.
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9.发明授权Circuit and method for varying a pulse width of an internal control signal during a test mode 失效在测试模式期间改变内部控制信号的脉冲宽度的电路和方法公开(公告)号：US06587978B1
公开(公告)日：2003-07-01
申请号：US08603943
申请日：1996-02-20
IPC分类号： G11C2900
CPC分类号： G11C29/50012 , G11C11/401 , G11C29/14
摘要： The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a pulse width of an internal control signal to stress the DRAM during a test mode.
摘要翻译： 本发明是具有在板上制造的电子测试键的动态随机存取存储器（DRAM）器件，并且是用于测试DRAM的方法。 电子测试键产生在测试模式期间影响内部控制信号的脉冲宽度变化以胁迫DRAM的信号。
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公开(公告)号：US06475851B1
公开(公告)日：2002-11-05
申请号：US09124478
申请日：1998-07-29
IPC分类号： H01L218238
CPC分类号： H01L21/765 , H01L21/823481 , H01L27/0207 , H01L27/088 , H01L27/10805 , Y10T307/839
摘要： Adjacent unassociated field-effect transistors are formed from a single continuous layer of uniformly doped material in a semiconductor substrate. An insulating layer is formed over the active layer. A number of gates in a conductive layer define the transistors. Forming a connection between one of the gates and a reference potential forms a boundary between the unassociated transistors across the active material by preventing carrier transport thereacross.
摘要翻译： 相邻的非相关场效应晶体管由半导体衬底中的均匀掺杂材料的单个连续层形成。 在有源层上形成绝缘层。 导电层中的多个栅极限定晶体管。 在一个栅极和参考电位之间形成连接，通过防止跨越其的载流子传输，形成跨过活性材料的非相关晶体管之间的边界。
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