公开(公告)号：US20180083051A1

公开(公告)日：2018-03-22

申请号：US15527792

申请日：2016-10-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yu-Cheng Chan ,  Shuai Zhang ,  Qi Liu

IPC: H01L27/12 ,  H01L21/66 ,  H01L29/786

CPC classification number: H01L27/1296 ,  G02F1/1362 ,  G02F2001/136254 ,  H01L21/77 ,  H01L22/12 ,  H01L22/34 ,  H01L23/544 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78675

Abstract: The present disclosure provides a test element unit, an array substrate, a display panel, a display apparatus and a corresponding manufacturing method. The test element unit includes: a plurality of layers of test patterns, each layer of test pattern including at least one test block and at least one capacitor being formed between test blocks located in different layers, and, two electrodes of each of capacitors being two test blocks located in different layers, respectively, so that it can determined whether or not corresponding components and devices formed in the display region meet requirements by detecting the test patterns formed in the test region.

公开(公告)号：US09837542B2

公开(公告)日：2017-12-05

申请号：US15104504

申请日：2015-07-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Chunping Long ,  Yu-Cheng Chan ,  Xiaoyong Lu ,  Xialong Li

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L29/78633 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26513 ,  H01L27/1222 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/78696

Abstract: A polycrystalline silicon thin-film transistor includes a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.

公开(公告)号：US20170133512A1

公开(公告)日：2017-05-11

申请号：US15104504

申请日：2015-07-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Chunping Long ,  Yu-Cheng Chan ,  Xiaoyong Lu ,  Xiaolong Li

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78633 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02667 ,  H01L21/26513 ,  H01L27/1222 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675 ,  H01L29/78696

Abstract: The disclosure provides a polycrystalline silicon thin-film transistor and a method for manufacturing the same as well as a display device. The polycrystalline silicon thin-film transistor comprises: a substrate; an isolation layer formed on the substrate; and a polycrystalline silicon active layer formed on the substrate and the isolation layer, with two source-drain ion implantation regions being formed at both sides of the active layer, wherein the edges at both ends of the isolation layer are within the edges at both ends of the active layer. In the polycrystalline silicon thin-film transistor and the method for manufacturing the same provided by the disclosure, it is possible to increase the grain size of the active layer, improve the grain uniformity in a channel region thereof, effectively prevent deterioration of characteristics of the active layer caused by backlight irradiation, and improve the reliability of the device.

公开(公告)号：US10020328B2

公开(公告)日：2018-07-10

申请号：US15527792

申请日：2016-10-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yu-Cheng Chan ,  Shuai Zhang ,  Qi Liu

IPC: H01L23/58 ,  H01L27/12 ,  H01L21/66 ,  H01L29/786

CPC classification number: H01L27/1296 ,  G02F1/1362 ,  G02F2001/136254 ,  H01L21/77 ,  H01L22/12 ,  H01L22/34 ,  H01L23/544 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/78675

Abstract: The present disclosure provides a test element unit, an array substrate, a display panel, a display apparatus and a corresponding manufacturing method. The test element unit includes: a plurality of layers of test patterns, each layer of test pattern including at least one test block and at least one capacitor being formed between test blocks located in different layers, and, two electrodes of each of capacitors being two test blocks located in different layers, respectively, so that it can determined whether or not corresponding components and devices formed in the display region meet requirements by detecting the test patterns formed in the test region.

公开(公告)号：US09673333B2

公开(公告)日：2017-06-06

申请号：US15122066

申请日：2016-02-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zheng Liu ,  Xiaoyong Lu ,  Xiaolong Li ,  Yu-Cheng Chan

IPC: H01L29/786 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L29/78621 ,  H01L27/02 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78645 ,  H01L29/78675 ,  H01L29/78696

Abstract: A method for fabricating a Polysilicon Thin-Film Transistor is provided. The method includes forming a polysilicon active layer, forming a first gate insulation layer and a first gate electrode sequentially on the active layer, conducting a first ion implantation process on the active layer by using the first gate electrode as a mask to form two doped regions at ends of the active layer, forming a second gate insulation layer and a second gate electrode sequentially on the first gate insulation layer and the first gate electrode, and conducting a second ion implantation process on the active layer by using the second gate electrode as another mask to form two source/drain implantation regions at two outer sides of the doped regions of the active layer. Accordingly, impurity concentration of the two doped regions is smaller than that of the two source/drain implantation regions.