公开(公告)号：US09673231B2

公开(公告)日：2017-06-06

申请号：US15233255

申请日：2016-08-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shi Shu ,  Feng Zhang ,  Yaohui Gu ,  Fang He ,  Feng Gu

IPC: H01L29/80 ,  H01L27/12 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1339 ,  H01L21/768 ,  H01L29/45

CPC classification number: H01L27/124 ,  G02F1/133345 ,  G02F1/133516 ,  G02F1/13394 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1288 ,  H01L29/458

Abstract: Embodiments of the disclosure provide an array substrate having via-hole conductive layer and display device. The array substrate includes: a thin film transistor; a passivation layer, covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; a via-hole conductive layer, covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode, and a reflectivity of the via-hole conductive layer being lower than a reflectivity of the drain electrode; and a pixel electrode, connected with the drain electrode through the via-hole conductive layer.

公开(公告)号：US10546885B2

公开(公告)日：2020-01-28

申请号：US15768634

申请日：2017-10-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shi Shu ,  Chuanxiang Xu ,  Teng Luo ,  Feng Gu ,  Bin Zhang

IPC: H01L27/12 ,  G02F1/1362 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/32 ,  G02F1/1343 ,  H01L21/02 ,  H01L21/30

Abstract: A method for fabricating a thin film transistor includes providing a substrate (100); forming a semiconductor layer (105) over the substrate (100); forming a source-drain metal layer (106) over the semiconductor layer (105); applying one patterning process to the semiconductor layer (105) and the source-drain metal layer (106) to form an active layer (1), a source electrode (2), and a drain electrode (3); forming a gate insulating layer (101) and an interlayer insulating layer (102) that cover the active layer (1), the source electrode (2), and the drain electrode (3); applying a patterning process to the interlayer insulating layer (102) to form a first window (10) in the interlayer insulating layer (102) to expose a portion of the gate insulating layer (101); and forming a gate electrode (4) in the first window (10). An orthogonal projection of the gate electrode (4) on the substrate (100) is in an orthogonal projection of the active layer (1) on the substrate (100).

公开(公告)号：US10698248B2

公开(公告)日：2020-06-30

申请号：US15810591

申请日：2017-11-13

Applicant: BOE Technology Group Co., Ltd.

Inventor： Shi Shu ,  Chuanxiang Xu ,  Teng Luo ,  Feng Gu

IPC: G02F1/1335 ,  G02F1/1339 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  G02F1/1333

Abstract: The present disclosure provides a counter substrate, a display panel, a display device, and fabricating method, further simplifying the fabricating process of the display panel by reducing the number of masking times required during the making of a spacer pattern and a frame light shielding pattern while achieving the frame light shielding function of the counter substrate and getting the counter substrate conductive with an array substrate. The fabricating method of the counter substrate comprises: forming a transparent electrode layer on a first base substrate; forming a black spacer pattern and a frame light shielding pattern at the same time on the transparent electrode layer, wherein the frame light shielding pattern comprises a first via hole that exposes a portion of the transparent electrode layer; and forming a conductive light shielding layer pattern in the first via hole.

公开(公告)号：US10504944B2

公开(公告)日：2019-12-10

申请号：US15768634

申请日：2017-10-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shi Shu ,  Chuanxiang Xu ,  Teng Luo ,  Feng Gu ,  Bin Zhang

IPC: H01L27/12 ,  G02F1/1362 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/32 ,  G02F1/1343 ,  H01L21/02 ,  H01L21/30

Abstract: A method for fabricating a thin film transistor includes providing a substrate (100); forming a semiconductor layer (105) over the substrate (100); forming a source-drain metal layer (106) over the semiconductor layer (105); applying one patterning process to the semiconductor layer (105) and the source-drain metal layer (106) to form an active layer (1), a source electrode (2), and a drain electrode (3); forming a gate insulating layer (101) and an interlayer insulating layer (102) that cover the active layer (1), the source electrode (2), and the drain electrode (3); applying a patterning process to the interlayer insulating layer (102) to form a first window (10) in the interlayer insulating layer (102) to expose a portion of the gate insulating layer (101); and forming a gate electrode (4) in the first window (10). An orthogonal projection of the gate electrode (4) on the substrate (100) is in an orthogonal projection of the active layer (1) on the substrate (100).

公开(公告)号：US09437487B2

公开(公告)日：2016-09-06

申请号：US14574721

申请日：2014-12-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shi Shu ,  Feng Zhang ,  Yaohui Gu ,  Fang He ,  Feng Gu

IPC: H01L21/00 ,  H01L21/768 ,  H01L27/12 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L27/124 ,  G02F1/133345 ,  G02F1/133516 ,  G02F1/13394 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1288 ,  H01L29/458

Abstract: Embodiments of the disclosure disclose an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate comprises: forming a thin film transistor; forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode; treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer.

Abstract translation: 本发明的实施例公开了阵列基板及其制造方法以及显示装置。 阵列基板的制造方法包括：形成薄膜晶体管; 形成覆盖所述薄膜晶体管的钝化层，所述钝化层具有通孔，所述通孔暴露所述薄膜晶体管的漏电极的至少一部分; 形成通孔导电层，所述通孔导电层覆盖在所述通孔露出并与所述漏电极连接的所述漏电极的所述部分; 处理通孔导电层，使得通孔导电层的反射率低于漏电极的反射率; 并且形成像素电极，所述像素电极通过所述通孔导电层与所述漏电极连接。

公开(公告)号：US20190067340A1

公开(公告)日：2019-02-28

申请号：US15768634

申请日：2017-10-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shi Shu ,  Chuanxiang Xu ,  Teng Luo ,  Feng Gu ,  Bin Zhang

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  G02F1/1368 ,  G02F1/1362

Abstract: A method for fabricating a thin film transistor includes providing a substrate (100); forming a semiconductor layer (105) over the substrate (100); forming a source-drain metal layer (106) over the semiconductor layer (105); applying one patterning process to the semiconductor layer (105) and the source-drain metal layer (106) to form an active layer (1), a source electrode (2), and a drain electrode (3); forming a gate insulating layer (101) and an interlayer insulating layer (102) that cover the active layer (1), the source electrode (2), and the drain electrode (3); applying a patterning process to the interlayer insulating layer (102) to form a first window (10) in the interlayer insulating layer (102) to expose a portion of the gate insulating layer (101); and forming a gate electrode (4) in the first window (10). An orthogonal projection of the gate electrode (4) on the substrate (100) is in an orthogonal projection of the active layer (1) on the substrate (100).

公开(公告)号：US10030197B2

公开(公告)日：2018-07-24

申请号：US14769097

申请日：2015-03-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng Gu

IPC: C09K13/08 ,  C03C15/00

Abstract: The invention provides an etching solution, comprising: 10 to 30 wt % of phosphoric acid; 2 to 20 wt % of nitric acid; 6 to 18 wt % of hydrofluoric acid; 5 to 10 wt % of hydrochloric acid; and water, wherein the weight percentages are based on the weight of the etching solution. The etching solution can be used for thinning the substrate in large-scale production, dissolving the precipitated impurities attached to the surface of the substrate after substrate thinning so as to remove effectively the impurities on the surface of the substrate, improve the qualified ratio and passed ratio of a product, and at the same time, provide the effective insurance for controlling the thickness of the substrate.