公开(公告)号：US20150299856A1

公开(公告)日：2015-10-22

申请号：US14625846

申请日：2015-02-19

Applicant: Applied Materials, Inc.

Inventor： Ning LI ,  Wenbo YAN ,  Victor NGUYEN ,  Cong TRINH ,  Mihaela BALSEANU ,  Li-Qun XIA

IPC: C23C16/455 ,  H01L21/3065

CPC classification number: C23C16/45534 ,  C23C16/045 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3065

Abstract: Embodiments disclosed herein generally relate to the processing of substrates, and more particularly, relate to methods for accurate control of film thickness using deposition-etch cycles. Particularly, embodiments of the present disclosure may be used in controlling film thickness during filling high aspect ratio features.

Abstract translation: 本文公开的实施例通常涉及衬底的处理，更具体地涉及使用沉积蚀刻循环来精确控制膜厚度的方法。 特别地，本公开的实施例可以用于在填充高纵横比特征期间控制膜厚度。

公开(公告)号：US20250079199A1

公开(公告)日：2025-03-06

申请号：US18458146

申请日：2023-08-29

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Sahil Jaykumar PATEL ,  Yu LEI ,  Wei LEI ,  Chih-Hsun HSU ,  Yi XU ,  Abulaiti HAIRISHA ,  Cong TRINH ,  Yixiong YANG ,  Ju Hyun OH ,  Aixi ZHANG ,  Xingyao GAO ,  Rongjun WANG

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/3213

Abstract: A method of selective metal removal via gradient oxidation for a gap-fill includes performing process cycles, each process cycle including placing a wafer having a semiconductor structure thereon into a first processing station, the semiconductor structure including a dielectric layer patterned with a feature formed therein and a seed layer formed on sidewalls and a bottom surface of the feature and a top surface of the dielectric layer, performing a reduction process on the wafer in the first processing station, performing a gradient oxidation process on the wafer in the second processing station, performing a gradient etch process on the wafer in the third processing station, and performing the gradient etch process on the wafer in the fourth processing station, wherein the first, second, third, and fourth processing stations are located in an interior volume of a processing chamber.

公开(公告)号：US20250006518A1

公开(公告)日：2025-01-02

申请号：US18753006

申请日：2024-06-25

Applicant: Applied Materials, Inc.

Inventor： Shiyu YUE ,  Wei LEI ,  Yu LEI ,  Ju Hyun OH ,  Zhimin QI ,  Sahil Jaykumar PATEL ,  Yi XU ,  Aixi ZHANG ,  Bingqian LIU ,  Cong TRINH ,  Xianmin TANG ,  Hayrensa ABLAT

IPC: H01L21/67 ,  H01L21/321 ,  H01L21/768 ,  H01L23/532

Abstract: Embodiments herein relate to a method, semiconductor device structures, and multi-chamber processing system for exposing a semiconductor device structure to an oxidizing plasma to form an oxide layer on at least one electrical connection formed in at least one feature formed within a dielectric layer of the semiconductor device structure, performing an etch process to remove the oxide layer and form an etch recess between a portion of the electrical connection and the dielectric layer At least a portion of the etch recess extends underneath at least a portion of the dielectric layer, and filling the at least one feature and the etch recess with a metal material.