公开(公告)号：US10535400B2

公开(公告)日：2020-01-14

申请号：US15939078

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： William R. Weier ,  Steven Frederick Schicht

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/22

Abstract: Systems, apparatuses, and methods for efficiently driving level shifted write data are described. In various embodiments, a level-shifting write driver combines a write data bit and a write mask bit that each use a first supply voltage to indicate a logic high level. During a write operation, the driver generates complementary values on two output nodes based on the write data bit. The output nodes use a second supply voltage greater than the first supply voltage. Before a write operation, the driver precharges each of the two output nodes to the second supply voltage. When the write clock enables a write operation and the write mask bit disables the write operation, the level-shifting write driver puts the two output nodes in a tri-state.

公开(公告)号：US10592367B2

公开(公告)日：2020-03-17

申请号：US15939089

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： Steven Frederick Schicht ,  William R. Weier

IPC: G06F11/00 ,  G06F11/20 ,  G06F3/06 ,  G11C7/10 ,  G11C29/00 ,  G11C11/419 ,  G11C29/12

Abstract: Systems, apparatuses, and methods for efficiently increasing reliability of memory accesses are described. In various embodiments, write data and write mask data are shifted by redundancy logic in a memory. The redundancy logic receives write data bits, which are segmented into one or more write groups in addition to one or more mask bits and one or more shift bits per write group. If the redundancy logic detects a first shift bit assigned to a first write group is asserted, then the redundancy logic selects a second mask bit assigned to a second write group different from the first write group. Otherwise, a first mask bit assigned to the first write group is selected. Following, the redundancy logic combines the selected mask bit with the first data bit of the first write group.

公开(公告)号：US20190087291A1

公开(公告)日：2019-03-21

申请号：US15939089

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： Steven Frederick Schicht ,  William R. Weier

IPC: G06F11/20 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for efficiently increasing reliability of memory accesses are described. In various embodiments, write data and write mask data are shifted by redundancy logic in a memory. The redundancy logic receives write data bits, which are segmented into one or more write groups in addition to one or more mask bits and one or more shift bits per write group. If the redundancy logic detects a first shift bit assigned to a first write group is asserted, then the redundancy logic selects a second mask bit assigned to a second write group different from the first write group. Otherwise, a first mask bit assigned to the first write group is selected. Following, the redundancy logic combines the selected mask bit with the first data bit of the first write group.

公开(公告)号：US20190080748A1

公开(公告)日：2019-03-14

申请号：US15939078

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： William R. Weier ,  Steven Frederick Schicht

IPC: G11C11/419 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C7/1009 ,  G11C7/1096 ,  G11C7/22 ,  G11C29/702 ,  G11C29/74

Abstract: Systems, apparatuses, and methods for efficiently driving level shifted write data are described. In various embodiments, a level-shifting write driver combines a write data bit and a write mask bit that each use a first supply voltage to indicate a logic high level. During a write operation, the driver generates complementary values on two output nodes based on the write data bit. The output nodes use a second supply voltage greater than the first supply voltage. Before a write operation, the driver precharges each of the two output nodes to the second supply voltage. When the write clock enables a write operation and the write mask bit disables the write operation, the level-shifting write driver puts the two output nodes in a tri-state.