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公开(公告)号：US11960739B1
公开(公告)日：2024-04-16
申请号：US17929191
申请日：2022-09-01
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , David A. Knopf , Satish B. Dulam , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C7/22 , G11C2207/2254
Abstract: The present disclosure is directed to a reference voltage calibration. An apparatus includes a memory and a memory controller including a calibration circuit configured to perform a reference voltage calibration to determine a reference voltage used to distinguish between logic values read from the memory. The reference voltage calibration comprises performing horizontal calibrations at different reference voltage values to determine a range of delay values applied to a data strobe signal at which valid data is read from the memory. The calibration includes determining scores corresponding to ones of the plurality of horizontal calibrations in which a score for a particular one of the plurality of horizontal calibrations is based on a corresponding range of delay values and a reference voltage margin. Thereafter, the calibration circuit selects a calibrated reference voltage based on the scores corresponding to ones of the plurality of horizontal calibrations.
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Patent Agency Ranking
公开(公告)号：US20240211151A1
公开(公告)日：2024-06-27
申请号：US18596046
申请日：2024-03-05
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Jingkui Zheng , David A. Knopf , Satish B. Dulam , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan
CPC classification number: G06F3/0632 , G06F3/0614 , G06F3/0658 , G06F3/0673 , G11C7/22 , G11C2207/2254
Abstract: An apparatus for performing a write data strobe concurrent with a reference voltage calibration is disclosed. A memory controller circuit is configured to convey a write clock signal to a memory. The memory controller circuit includes a calibration circuit configured to send a first command to memory to initiate a calibration of the write clock signal and, after an amount of time has elapsed, receive a calibration value from the memory. The memory controller further includes a delay circuit configured to apply a delay to the write clock signal, wherein the calibration circuit is configured to complete calibration of the write clock signal by adjusting the delay applied to the write clock signal in accordance with the calibration value. The calibration circuit is further configured to perform a reference voltage calibration concurrent with the calibration of the write clock signal.
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公开(公告)号：US20220189519A1
公开(公告)日：2022-06-16
申请号：US17646741
申请日：2022-01-03
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan , Naveen Kumar Korada
Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
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公开(公告)号：US11217285B1
公开(公告)日：2022-01-04
申请号：US16986116
申请日：2020-08-05
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan , Naveen Kumar Korada
Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
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公开(公告)号：US20240062792A1
公开(公告)日：2024-02-22
申请号：US18455385
申请日：2023-08-24
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan , Naveen Kumar Korada
CPC classification number: G11C7/22 , G06F11/1076 , G11C7/10 , G11C2207/2254
Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibration, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
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公开(公告)号：US11776597B2
公开(公告)日：2023-10-03
申请号：US17646741
申请日：2022-01-03
Applicant: Apple Inc.
Inventor： Robert E. Jeter , Rakesh L. Notani , Kai Lun Hsiung , Venkata Ramana Malladi , Rahul Ranjan , Naveen Kumar Korada
CPC classification number: G11C7/22 , G06F11/1076 , G11C7/10 , G11C2207/2254
Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.
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