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    Connection pad for embedded components in PCB packaging
    2.
    发明授权
    Connection pad for embedded components in PCB packaging 有权

    公开(公告)号：US10455707B1

    公开(公告)日：2019-10-22

    申请号：US16100456

    申请日：2018-08-10

    Applicant: Apple Inc.

    Inventor： Kenneth Leland Kiplinger ,  Mark J. Beesley ,  Shawn Xavier Arnold ,  Shyam Harindralal Ratnayake ,  Meng Chi Lee

    IPC: H05K3/34 ,  H05K3/46 ,  H05K1/11 ,  H05K1/18 ,  H01L23/498

    Abstract: Described herein are printed circuit boards (PCBs), PCB assemblies, and methods of manufacture thereof, which allow free placement of electrical components. The PCBs may have electrical pads that may couple to components through via-based connections and without the use of solder. The electrical components may be physically attached to the PCBs through tight fitting, lamination, and/or the use of adhesives. The distance between adjacent vias may be reduced, as accidental short-circuit risks due to solder bridging and similar effects are mitigated when the soldering process is bypassed. The PCB design and component placement may be flexible as to allow the use of electrical components with custom shape and/or customized terminal placement.

    Three-Dimensional (3D) Copper in Printed Circuit Boards
    4.
    发明申请
    Three-Dimensional (3D) Copper in Printed Circuit Boards 有权

    公开(公告)号：US20220095455A1

    公开(公告)日：2022-03-24

    申请号：US17119126

    申请日：2020-12-11

    Applicant: Apple Inc.

    Inventor： Anne M. Mason ,  Chad O. Simpson ,  William Hannon ,  Mark J. Beesley

    IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42

    Abstract: Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.

    Segmented via for vertical PCB interconnect
    6.
    发明授权
    Segmented via for vertical PCB interconnect 有权

    公开(公告)号：US10420213B2

    公开(公告)日：2019-09-17

    申请号：US15696102

    申请日：2017-09-05

    Applicant: Apple Inc.

    Inventor： Mark J. Beesley ,  Albert A. Onderick, II ,  Anne M. Mason ,  Craig A. Gammel ,  Shawn X. Arnold

    IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K1/14

    Abstract: Printed circuit boards having an increased density of vertical interconnect paths, as well as methods for their manufacture. One example may provide a printed circuit board having an increased density of vertical interconnect paths by forming a plurality of segmented vias. The segmented vias may extend through interior layers of the printed circuit board. The segmented vias may be formed of portions of vias in the interior layers of the printed circuit board. An area between three or more segmented vias may be filled with resin or other material or materials.

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