公开(公告)号：US09904624B1

公开(公告)日：2018-02-27

申请号：US15093173

申请日：2016-04-07

Applicant: Apple Inc.

Inventor： Tyler J. Huberty ,  Stephan G. Meier ,  Khubaib Khubaib

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F12/0811 ,  G06F12/0875 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/602

Abstract: In an embodiment, a system may include multiple processors and a cache coupled to the processors. Each processor includes a data cache and a prefetch circuit that may be configured to generate prefetch requests. Each processor may also generate memory operations responsive to cache misses in the data cache. Each processor may transmit the prefetch requests and memory operations to the cache. The cache may queue the memory operations and prefetch requests, and may be configured to detect, on a per-processor basis, occupancy in the queue of memory requests and low confidence prefetch requests from the processor. The cache may determine if the per-processor occupancies exceed one or more thresholds, and may generate a throttle control to the processors responsive to the occupancies. In an embodiment, the cache may generate the throttle control responsive to a history of the last N samples of the occupancies.